[llvm] b9b96ad - [X86][SSE] Add SSE41 coverage for fmaxnum/fminnum tests
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 10 04:26:02 PDT 2020
Author: Simon Pilgrim
Date: 2020-03-10T11:18:27Z
New Revision: b9b96adcf574f2bbc8133e61431e7ea839a1666b
URL: https://github.com/llvm/llvm-project/commit/b9b96adcf574f2bbc8133e61431e7ea839a1666b
DIFF: https://github.com/llvm/llvm-project/commit/b9b96adcf574f2bbc8133e61431e7ea839a1666b.diff
LOG: [X86][SSE] Add SSE41 coverage for fmaxnum/fminnum tests
Added:
Modified:
llvm/test/CodeGen/X86/fmaxnum.ll
llvm/test/CodeGen/X86/fminnum.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/fmaxnum.ll b/llvm/test/CodeGen/X86/fmaxnum.ll
index 23de2667a3ec..2a7bb25164d3 100644
--- a/llvm/test/CodeGen/X86/fmaxnum.ll
+++ b/llvm/test/CodeGen/X86/fmaxnum.ll
@@ -1,7 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=sse2 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
-; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx < %s | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX1
-; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx512f < %s | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE,SSE4
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX,AVX1
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
declare float @fmaxf(float, float)
declare double @fmax(double, double)
@@ -189,15 +190,24 @@ define x86_fp80 @test_intrinsic_fmaxl(x86_fp80 %x, x86_fp80 %y) {
}
define <2 x float> @test_intrinsic_fmax_v2f32(<2 x float> %x, <2 x float> %y) {
-; SSE-LABEL: test_intrinsic_fmax_v2f32:
-; SSE: # %bb.0:
-; SSE-NEXT: movaps %xmm1, %xmm2
-; SSE-NEXT: maxps %xmm0, %xmm2
-; SSE-NEXT: cmpunordps %xmm0, %xmm0
-; SSE-NEXT: andps %xmm0, %xmm1
-; SSE-NEXT: andnps %xmm2, %xmm0
-; SSE-NEXT: orps %xmm1, %xmm0
-; SSE-NEXT: retq
+; SSE2-LABEL: test_intrinsic_fmax_v2f32:
+; SSE2: # %bb.0:
+; SSE2-NEXT: movaps %xmm1, %xmm2
+; SSE2-NEXT: maxps %xmm0, %xmm2
+; SSE2-NEXT: cmpunordps %xmm0, %xmm0
+; SSE2-NEXT: andps %xmm0, %xmm1
+; SSE2-NEXT: andnps %xmm2, %xmm0
+; SSE2-NEXT: orps %xmm1, %xmm0
+; SSE2-NEXT: retq
+;
+; SSE4-LABEL: test_intrinsic_fmax_v2f32:
+; SSE4: # %bb.0:
+; SSE4-NEXT: movaps %xmm1, %xmm2
+; SSE4-NEXT: maxps %xmm0, %xmm2
+; SSE4-NEXT: cmpunordps %xmm0, %xmm0
+; SSE4-NEXT: blendvps %xmm0, %xmm1, %xmm2
+; SSE4-NEXT: movaps %xmm2, %xmm0
+; SSE4-NEXT: retq
;
; AVX-LABEL: test_intrinsic_fmax_v2f32:
; AVX: # %bb.0:
@@ -210,15 +220,24 @@ define <2 x float> @test_intrinsic_fmax_v2f32(<2 x float> %x, <2 x float> %y) {
}
define <4 x float> @test_intrinsic_fmax_v4f32(<4 x float> %x, <4 x float> %y) {
-; SSE-LABEL: test_intrinsic_fmax_v4f32:
-; SSE: # %bb.0:
-; SSE-NEXT: movaps %xmm1, %xmm2
-; SSE-NEXT: maxps %xmm0, %xmm2
-; SSE-NEXT: cmpunordps %xmm0, %xmm0
-; SSE-NEXT: andps %xmm0, %xmm1
-; SSE-NEXT: andnps %xmm2, %xmm0
-; SSE-NEXT: orps %xmm1, %xmm0
-; SSE-NEXT: retq
+; SSE2-LABEL: test_intrinsic_fmax_v4f32:
+; SSE2: # %bb.0:
+; SSE2-NEXT: movaps %xmm1, %xmm2
+; SSE2-NEXT: maxps %xmm0, %xmm2
+; SSE2-NEXT: cmpunordps %xmm0, %xmm0
+; SSE2-NEXT: andps %xmm0, %xmm1
+; SSE2-NEXT: andnps %xmm2, %xmm0
+; SSE2-NEXT: orps %xmm1, %xmm0
+; SSE2-NEXT: retq
+;
+; SSE4-LABEL: test_intrinsic_fmax_v4f32:
+; SSE4: # %bb.0:
+; SSE4-NEXT: movaps %xmm1, %xmm2
+; SSE4-NEXT: maxps %xmm0, %xmm2
+; SSE4-NEXT: cmpunordps %xmm0, %xmm0
+; SSE4-NEXT: blendvps %xmm0, %xmm1, %xmm2
+; SSE4-NEXT: movaps %xmm2, %xmm0
+; SSE4-NEXT: retq
;
; AVX-LABEL: test_intrinsic_fmax_v4f32:
; AVX: # %bb.0:
@@ -231,21 +250,36 @@ define <4 x float> @test_intrinsic_fmax_v4f32(<4 x float> %x, <4 x float> %y) {
}
define <8 x float> @test_intrinsic_fmax_v8f32(<8 x float> %x, <8 x float> %y) {
-; SSE-LABEL: test_intrinsic_fmax_v8f32:
-; SSE: # %bb.0:
-; SSE-NEXT: movaps %xmm2, %xmm4
-; SSE-NEXT: maxps %xmm0, %xmm4
-; SSE-NEXT: cmpunordps %xmm0, %xmm0
-; SSE-NEXT: andps %xmm0, %xmm2
-; SSE-NEXT: andnps %xmm4, %xmm0
-; SSE-NEXT: orps %xmm2, %xmm0
-; SSE-NEXT: movaps %xmm3, %xmm2
-; SSE-NEXT: maxps %xmm1, %xmm2
-; SSE-NEXT: cmpunordps %xmm1, %xmm1
-; SSE-NEXT: andps %xmm1, %xmm3
-; SSE-NEXT: andnps %xmm2, %xmm1
-; SSE-NEXT: orps %xmm3, %xmm1
-; SSE-NEXT: retq
+; SSE2-LABEL: test_intrinsic_fmax_v8f32:
+; SSE2: # %bb.0:
+; SSE2-NEXT: movaps %xmm2, %xmm4
+; SSE2-NEXT: maxps %xmm0, %xmm4
+; SSE2-NEXT: cmpunordps %xmm0, %xmm0
+; SSE2-NEXT: andps %xmm0, %xmm2
+; SSE2-NEXT: andnps %xmm4, %xmm0
+; SSE2-NEXT: orps %xmm2, %xmm0
+; SSE2-NEXT: movaps %xmm3, %xmm2
+; SSE2-NEXT: maxps %xmm1, %xmm2
+; SSE2-NEXT: cmpunordps %xmm1, %xmm1
+; SSE2-NEXT: andps %xmm1, %xmm3
+; SSE2-NEXT: andnps %xmm2, %xmm1
+; SSE2-NEXT: orps %xmm3, %xmm1
+; SSE2-NEXT: retq
+;
+; SSE4-LABEL: test_intrinsic_fmax_v8f32:
+; SSE4: # %bb.0:
+; SSE4-NEXT: movaps %xmm1, %xmm5
+; SSE4-NEXT: movaps %xmm2, %xmm4
+; SSE4-NEXT: maxps %xmm0, %xmm4
+; SSE4-NEXT: cmpunordps %xmm0, %xmm0
+; SSE4-NEXT: blendvps %xmm0, %xmm2, %xmm4
+; SSE4-NEXT: movaps %xmm3, %xmm1
+; SSE4-NEXT: maxps %xmm5, %xmm1
+; SSE4-NEXT: cmpunordps %xmm5, %xmm5
+; SSE4-NEXT: movaps %xmm5, %xmm0
+; SSE4-NEXT: blendvps %xmm0, %xmm3, %xmm1
+; SSE4-NEXT: movaps %xmm4, %xmm0
+; SSE4-NEXT: retq
;
; AVX-LABEL: test_intrinsic_fmax_v8f32:
; AVX: # %bb.0:
@@ -258,33 +292,60 @@ define <8 x float> @test_intrinsic_fmax_v8f32(<8 x float> %x, <8 x float> %y) {
}
define <16 x float> @test_intrinsic_fmax_v16f32(<16 x float> %x, <16 x float> %y) {
-; SSE-LABEL: test_intrinsic_fmax_v16f32:
-; SSE: # %bb.0:
-; SSE-NEXT: movaps %xmm4, %xmm8
-; SSE-NEXT: maxps %xmm0, %xmm8
-; SSE-NEXT: cmpunordps %xmm0, %xmm0
-; SSE-NEXT: andps %xmm0, %xmm4
-; SSE-NEXT: andnps %xmm8, %xmm0
-; SSE-NEXT: orps %xmm4, %xmm0
-; SSE-NEXT: movaps %xmm5, %xmm4
-; SSE-NEXT: maxps %xmm1, %xmm4
-; SSE-NEXT: cmpunordps %xmm1, %xmm1
-; SSE-NEXT: andps %xmm1, %xmm5
-; SSE-NEXT: andnps %xmm4, %xmm1
-; SSE-NEXT: orps %xmm5, %xmm1
-; SSE-NEXT: movaps %xmm6, %xmm4
-; SSE-NEXT: maxps %xmm2, %xmm4
-; SSE-NEXT: cmpunordps %xmm2, %xmm2
-; SSE-NEXT: andps %xmm2, %xmm6
-; SSE-NEXT: andnps %xmm4, %xmm2
-; SSE-NEXT: orps %xmm6, %xmm2
-; SSE-NEXT: movaps %xmm7, %xmm4
-; SSE-NEXT: maxps %xmm3, %xmm4
-; SSE-NEXT: cmpunordps %xmm3, %xmm3
-; SSE-NEXT: andps %xmm3, %xmm7
-; SSE-NEXT: andnps %xmm4, %xmm3
-; SSE-NEXT: orps %xmm7, %xmm3
-; SSE-NEXT: retq
+; SSE2-LABEL: test_intrinsic_fmax_v16f32:
+; SSE2: # %bb.0:
+; SSE2-NEXT: movaps %xmm4, %xmm8
+; SSE2-NEXT: maxps %xmm0, %xmm8
+; SSE2-NEXT: cmpunordps %xmm0, %xmm0
+; SSE2-NEXT: andps %xmm0, %xmm4
+; SSE2-NEXT: andnps %xmm8, %xmm0
+; SSE2-NEXT: orps %xmm4, %xmm0
+; SSE2-NEXT: movaps %xmm5, %xmm4
+; SSE2-NEXT: maxps %xmm1, %xmm4
+; SSE2-NEXT: cmpunordps %xmm1, %xmm1
+; SSE2-NEXT: andps %xmm1, %xmm5
+; SSE2-NEXT: andnps %xmm4, %xmm1
+; SSE2-NEXT: orps %xmm5, %xmm1
+; SSE2-NEXT: movaps %xmm6, %xmm4
+; SSE2-NEXT: maxps %xmm2, %xmm4
+; SSE2-NEXT: cmpunordps %xmm2, %xmm2
+; SSE2-NEXT: andps %xmm2, %xmm6
+; SSE2-NEXT: andnps %xmm4, %xmm2
+; SSE2-NEXT: orps %xmm6, %xmm2
+; SSE2-NEXT: movaps %xmm7, %xmm4
+; SSE2-NEXT: maxps %xmm3, %xmm4
+; SSE2-NEXT: cmpunordps %xmm3, %xmm3
+; SSE2-NEXT: andps %xmm3, %xmm7
+; SSE2-NEXT: andnps %xmm4, %xmm3
+; SSE2-NEXT: orps %xmm7, %xmm3
+; SSE2-NEXT: retq
+;
+; SSE4-LABEL: test_intrinsic_fmax_v16f32:
+; SSE4: # %bb.0:
+; SSE4-NEXT: movaps %xmm3, %xmm8
+; SSE4-NEXT: movaps %xmm2, %xmm9
+; SSE4-NEXT: movaps %xmm1, %xmm2
+; SSE4-NEXT: movaps %xmm4, %xmm10
+; SSE4-NEXT: maxps %xmm0, %xmm10
+; SSE4-NEXT: cmpunordps %xmm0, %xmm0
+; SSE4-NEXT: blendvps %xmm0, %xmm4, %xmm10
+; SSE4-NEXT: movaps %xmm5, %xmm1
+; SSE4-NEXT: maxps %xmm2, %xmm1
+; SSE4-NEXT: cmpunordps %xmm2, %xmm2
+; SSE4-NEXT: movaps %xmm2, %xmm0
+; SSE4-NEXT: blendvps %xmm0, %xmm5, %xmm1
+; SSE4-NEXT: movaps %xmm6, %xmm2
+; SSE4-NEXT: maxps %xmm9, %xmm2
+; SSE4-NEXT: cmpunordps %xmm9, %xmm9
+; SSE4-NEXT: movaps %xmm9, %xmm0
+; SSE4-NEXT: blendvps %xmm0, %xmm6, %xmm2
+; SSE4-NEXT: movaps %xmm7, %xmm3
+; SSE4-NEXT: maxps %xmm8, %xmm3
+; SSE4-NEXT: cmpunordps %xmm8, %xmm8
+; SSE4-NEXT: movaps %xmm8, %xmm0
+; SSE4-NEXT: blendvps %xmm0, %xmm7, %xmm3
+; SSE4-NEXT: movaps %xmm10, %xmm0
+; SSE4-NEXT: retq
;
; AVX1-LABEL: test_intrinsic_fmax_v16f32:
; AVX1: # %bb.0:
@@ -308,15 +369,24 @@ define <16 x float> @test_intrinsic_fmax_v16f32(<16 x float> %x, <16 x float> %y
}
define <2 x double> @test_intrinsic_fmax_v2f64(<2 x double> %x, <2 x double> %y) {
-; SSE-LABEL: test_intrinsic_fmax_v2f64:
-; SSE: # %bb.0:
-; SSE-NEXT: movapd %xmm1, %xmm2
-; SSE-NEXT: maxpd %xmm0, %xmm2
-; SSE-NEXT: cmpunordpd %xmm0, %xmm0
-; SSE-NEXT: andpd %xmm0, %xmm1
-; SSE-NEXT: andnpd %xmm2, %xmm0
-; SSE-NEXT: orpd %xmm1, %xmm0
-; SSE-NEXT: retq
+; SSE2-LABEL: test_intrinsic_fmax_v2f64:
+; SSE2: # %bb.0:
+; SSE2-NEXT: movapd %xmm1, %xmm2
+; SSE2-NEXT: maxpd %xmm0, %xmm2
+; SSE2-NEXT: cmpunordpd %xmm0, %xmm0
+; SSE2-NEXT: andpd %xmm0, %xmm1
+; SSE2-NEXT: andnpd %xmm2, %xmm0
+; SSE2-NEXT: orpd %xmm1, %xmm0
+; SSE2-NEXT: retq
+;
+; SSE4-LABEL: test_intrinsic_fmax_v2f64:
+; SSE4: # %bb.0:
+; SSE4-NEXT: movapd %xmm1, %xmm2
+; SSE4-NEXT: maxpd %xmm0, %xmm2
+; SSE4-NEXT: cmpunordpd %xmm0, %xmm0
+; SSE4-NEXT: blendvpd %xmm0, %xmm1, %xmm2
+; SSE4-NEXT: movapd %xmm2, %xmm0
+; SSE4-NEXT: retq
;
; AVX-LABEL: test_intrinsic_fmax_v2f64:
; AVX: # %bb.0:
@@ -329,21 +399,36 @@ define <2 x double> @test_intrinsic_fmax_v2f64(<2 x double> %x, <2 x double> %y)
}
define <4 x double> @test_intrinsic_fmax_v4f64(<4 x double> %x, <4 x double> %y) {
-; SSE-LABEL: test_intrinsic_fmax_v4f64:
-; SSE: # %bb.0:
-; SSE-NEXT: movapd %xmm2, %xmm4
-; SSE-NEXT: maxpd %xmm0, %xmm4
-; SSE-NEXT: cmpunordpd %xmm0, %xmm0
-; SSE-NEXT: andpd %xmm0, %xmm2
-; SSE-NEXT: andnpd %xmm4, %xmm0
-; SSE-NEXT: orpd %xmm2, %xmm0
-; SSE-NEXT: movapd %xmm3, %xmm2
-; SSE-NEXT: maxpd %xmm1, %xmm2
-; SSE-NEXT: cmpunordpd %xmm1, %xmm1
-; SSE-NEXT: andpd %xmm1, %xmm3
-; SSE-NEXT: andnpd %xmm2, %xmm1
-; SSE-NEXT: orpd %xmm3, %xmm1
-; SSE-NEXT: retq
+; SSE2-LABEL: test_intrinsic_fmax_v4f64:
+; SSE2: # %bb.0:
+; SSE2-NEXT: movapd %xmm2, %xmm4
+; SSE2-NEXT: maxpd %xmm0, %xmm4
+; SSE2-NEXT: cmpunordpd %xmm0, %xmm0
+; SSE2-NEXT: andpd %xmm0, %xmm2
+; SSE2-NEXT: andnpd %xmm4, %xmm0
+; SSE2-NEXT: orpd %xmm2, %xmm0
+; SSE2-NEXT: movapd %xmm3, %xmm2
+; SSE2-NEXT: maxpd %xmm1, %xmm2
+; SSE2-NEXT: cmpunordpd %xmm1, %xmm1
+; SSE2-NEXT: andpd %xmm1, %xmm3
+; SSE2-NEXT: andnpd %xmm2, %xmm1
+; SSE2-NEXT: orpd %xmm3, %xmm1
+; SSE2-NEXT: retq
+;
+; SSE4-LABEL: test_intrinsic_fmax_v4f64:
+; SSE4: # %bb.0:
+; SSE4-NEXT: movapd %xmm1, %xmm5
+; SSE4-NEXT: movapd %xmm2, %xmm4
+; SSE4-NEXT: maxpd %xmm0, %xmm4
+; SSE4-NEXT: cmpunordpd %xmm0, %xmm0
+; SSE4-NEXT: blendvpd %xmm0, %xmm2, %xmm4
+; SSE4-NEXT: movapd %xmm3, %xmm1
+; SSE4-NEXT: maxpd %xmm5, %xmm1
+; SSE4-NEXT: cmpunordpd %xmm5, %xmm5
+; SSE4-NEXT: movapd %xmm5, %xmm0
+; SSE4-NEXT: blendvpd %xmm0, %xmm3, %xmm1
+; SSE4-NEXT: movapd %xmm4, %xmm0
+; SSE4-NEXT: retq
;
; AVX-LABEL: test_intrinsic_fmax_v4f64:
; AVX: # %bb.0:
@@ -356,33 +441,60 @@ define <4 x double> @test_intrinsic_fmax_v4f64(<4 x double> %x, <4 x double> %y)
}
define <8 x double> @test_intrinsic_fmax_v8f64(<8 x double> %x, <8 x double> %y) {
-; SSE-LABEL: test_intrinsic_fmax_v8f64:
-; SSE: # %bb.0:
-; SSE-NEXT: movapd %xmm4, %xmm8
-; SSE-NEXT: maxpd %xmm0, %xmm8
-; SSE-NEXT: cmpunordpd %xmm0, %xmm0
-; SSE-NEXT: andpd %xmm0, %xmm4
-; SSE-NEXT: andnpd %xmm8, %xmm0
-; SSE-NEXT: orpd %xmm4, %xmm0
-; SSE-NEXT: movapd %xmm5, %xmm4
-; SSE-NEXT: maxpd %xmm1, %xmm4
-; SSE-NEXT: cmpunordpd %xmm1, %xmm1
-; SSE-NEXT: andpd %xmm1, %xmm5
-; SSE-NEXT: andnpd %xmm4, %xmm1
-; SSE-NEXT: orpd %xmm5, %xmm1
-; SSE-NEXT: movapd %xmm6, %xmm4
-; SSE-NEXT: maxpd %xmm2, %xmm4
-; SSE-NEXT: cmpunordpd %xmm2, %xmm2
-; SSE-NEXT: andpd %xmm2, %xmm6
-; SSE-NEXT: andnpd %xmm4, %xmm2
-; SSE-NEXT: orpd %xmm6, %xmm2
-; SSE-NEXT: movapd %xmm7, %xmm4
-; SSE-NEXT: maxpd %xmm3, %xmm4
-; SSE-NEXT: cmpunordpd %xmm3, %xmm3
-; SSE-NEXT: andpd %xmm3, %xmm7
-; SSE-NEXT: andnpd %xmm4, %xmm3
-; SSE-NEXT: orpd %xmm7, %xmm3
-; SSE-NEXT: retq
+; SSE2-LABEL: test_intrinsic_fmax_v8f64:
+; SSE2: # %bb.0:
+; SSE2-NEXT: movapd %xmm4, %xmm8
+; SSE2-NEXT: maxpd %xmm0, %xmm8
+; SSE2-NEXT: cmpunordpd %xmm0, %xmm0
+; SSE2-NEXT: andpd %xmm0, %xmm4
+; SSE2-NEXT: andnpd %xmm8, %xmm0
+; SSE2-NEXT: orpd %xmm4, %xmm0
+; SSE2-NEXT: movapd %xmm5, %xmm4
+; SSE2-NEXT: maxpd %xmm1, %xmm4
+; SSE2-NEXT: cmpunordpd %xmm1, %xmm1
+; SSE2-NEXT: andpd %xmm1, %xmm5
+; SSE2-NEXT: andnpd %xmm4, %xmm1
+; SSE2-NEXT: orpd %xmm5, %xmm1
+; SSE2-NEXT: movapd %xmm6, %xmm4
+; SSE2-NEXT: maxpd %xmm2, %xmm4
+; SSE2-NEXT: cmpunordpd %xmm2, %xmm2
+; SSE2-NEXT: andpd %xmm2, %xmm6
+; SSE2-NEXT: andnpd %xmm4, %xmm2
+; SSE2-NEXT: orpd %xmm6, %xmm2
+; SSE2-NEXT: movapd %xmm7, %xmm4
+; SSE2-NEXT: maxpd %xmm3, %xmm4
+; SSE2-NEXT: cmpunordpd %xmm3, %xmm3
+; SSE2-NEXT: andpd %xmm3, %xmm7
+; SSE2-NEXT: andnpd %xmm4, %xmm3
+; SSE2-NEXT: orpd %xmm7, %xmm3
+; SSE2-NEXT: retq
+;
+; SSE4-LABEL: test_intrinsic_fmax_v8f64:
+; SSE4: # %bb.0:
+; SSE4-NEXT: movapd %xmm3, %xmm8
+; SSE4-NEXT: movapd %xmm2, %xmm9
+; SSE4-NEXT: movapd %xmm1, %xmm2
+; SSE4-NEXT: movapd %xmm4, %xmm10
+; SSE4-NEXT: maxpd %xmm0, %xmm10
+; SSE4-NEXT: cmpunordpd %xmm0, %xmm0
+; SSE4-NEXT: blendvpd %xmm0, %xmm4, %xmm10
+; SSE4-NEXT: movapd %xmm5, %xmm1
+; SSE4-NEXT: maxpd %xmm2, %xmm1
+; SSE4-NEXT: cmpunordpd %xmm2, %xmm2
+; SSE4-NEXT: movapd %xmm2, %xmm0
+; SSE4-NEXT: blendvpd %xmm0, %xmm5, %xmm1
+; SSE4-NEXT: movapd %xmm6, %xmm2
+; SSE4-NEXT: maxpd %xmm9, %xmm2
+; SSE4-NEXT: cmpunordpd %xmm9, %xmm9
+; SSE4-NEXT: movapd %xmm9, %xmm0
+; SSE4-NEXT: blendvpd %xmm0, %xmm6, %xmm2
+; SSE4-NEXT: movapd %xmm7, %xmm3
+; SSE4-NEXT: maxpd %xmm8, %xmm3
+; SSE4-NEXT: cmpunordpd %xmm8, %xmm8
+; SSE4-NEXT: movapd %xmm8, %xmm0
+; SSE4-NEXT: blendvpd %xmm0, %xmm7, %xmm3
+; SSE4-NEXT: movapd %xmm10, %xmm0
+; SSE4-NEXT: retq
;
; AVX1-LABEL: test_intrinsic_fmax_v8f64:
; AVX1: # %bb.0:
diff --git a/llvm/test/CodeGen/X86/fminnum.ll b/llvm/test/CodeGen/X86/fminnum.ll
index 1667a5cd0a75..fc4c48686a95 100644
--- a/llvm/test/CodeGen/X86/fminnum.ll
+++ b/llvm/test/CodeGen/X86/fminnum.ll
@@ -1,7 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=sse2 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
-; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx < %s | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX1
-; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx512f < %s | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE,SSE4
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX,AVX1
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
declare float @fminf(float, float)
declare double @fmin(double, double)
@@ -189,15 +190,24 @@ define x86_fp80 @test_intrinsic_fminl(x86_fp80 %x, x86_fp80 %y) {
}
define <2 x float> @test_intrinsic_fmin_v2f32(<2 x float> %x, <2 x float> %y) {
-; SSE-LABEL: test_intrinsic_fmin_v2f32:
-; SSE: # %bb.0:
-; SSE-NEXT: movaps %xmm1, %xmm2
-; SSE-NEXT: minps %xmm0, %xmm2
-; SSE-NEXT: cmpunordps %xmm0, %xmm0
-; SSE-NEXT: andps %xmm0, %xmm1
-; SSE-NEXT: andnps %xmm2, %xmm0
-; SSE-NEXT: orps %xmm1, %xmm0
-; SSE-NEXT: retq
+; SSE2-LABEL: test_intrinsic_fmin_v2f32:
+; SSE2: # %bb.0:
+; SSE2-NEXT: movaps %xmm1, %xmm2
+; SSE2-NEXT: minps %xmm0, %xmm2
+; SSE2-NEXT: cmpunordps %xmm0, %xmm0
+; SSE2-NEXT: andps %xmm0, %xmm1
+; SSE2-NEXT: andnps %xmm2, %xmm0
+; SSE2-NEXT: orps %xmm1, %xmm0
+; SSE2-NEXT: retq
+;
+; SSE4-LABEL: test_intrinsic_fmin_v2f32:
+; SSE4: # %bb.0:
+; SSE4-NEXT: movaps %xmm1, %xmm2
+; SSE4-NEXT: minps %xmm0, %xmm2
+; SSE4-NEXT: cmpunordps %xmm0, %xmm0
+; SSE4-NEXT: blendvps %xmm0, %xmm1, %xmm2
+; SSE4-NEXT: movaps %xmm2, %xmm0
+; SSE4-NEXT: retq
;
; AVX-LABEL: test_intrinsic_fmin_v2f32:
; AVX: # %bb.0:
@@ -210,15 +220,24 @@ define <2 x float> @test_intrinsic_fmin_v2f32(<2 x float> %x, <2 x float> %y) {
}
define <4 x float> @test_intrinsic_fmin_v4f32(<4 x float> %x, <4 x float> %y) {
-; SSE-LABEL: test_intrinsic_fmin_v4f32:
-; SSE: # %bb.0:
-; SSE-NEXT: movaps %xmm1, %xmm2
-; SSE-NEXT: minps %xmm0, %xmm2
-; SSE-NEXT: cmpunordps %xmm0, %xmm0
-; SSE-NEXT: andps %xmm0, %xmm1
-; SSE-NEXT: andnps %xmm2, %xmm0
-; SSE-NEXT: orps %xmm1, %xmm0
-; SSE-NEXT: retq
+; SSE2-LABEL: test_intrinsic_fmin_v4f32:
+; SSE2: # %bb.0:
+; SSE2-NEXT: movaps %xmm1, %xmm2
+; SSE2-NEXT: minps %xmm0, %xmm2
+; SSE2-NEXT: cmpunordps %xmm0, %xmm0
+; SSE2-NEXT: andps %xmm0, %xmm1
+; SSE2-NEXT: andnps %xmm2, %xmm0
+; SSE2-NEXT: orps %xmm1, %xmm0
+; SSE2-NEXT: retq
+;
+; SSE4-LABEL: test_intrinsic_fmin_v4f32:
+; SSE4: # %bb.0:
+; SSE4-NEXT: movaps %xmm1, %xmm2
+; SSE4-NEXT: minps %xmm0, %xmm2
+; SSE4-NEXT: cmpunordps %xmm0, %xmm0
+; SSE4-NEXT: blendvps %xmm0, %xmm1, %xmm2
+; SSE4-NEXT: movaps %xmm2, %xmm0
+; SSE4-NEXT: retq
;
; AVX-LABEL: test_intrinsic_fmin_v4f32:
; AVX: # %bb.0:
@@ -231,21 +250,36 @@ define <4 x float> @test_intrinsic_fmin_v4f32(<4 x float> %x, <4 x float> %y) {
}
define <8 x float> @test_intrinsic_fmin_v8f32(<8 x float> %x, <8 x float> %y) {
-; SSE-LABEL: test_intrinsic_fmin_v8f32:
-; SSE: # %bb.0:
-; SSE-NEXT: movaps %xmm2, %xmm4
-; SSE-NEXT: minps %xmm0, %xmm4
-; SSE-NEXT: cmpunordps %xmm0, %xmm0
-; SSE-NEXT: andps %xmm0, %xmm2
-; SSE-NEXT: andnps %xmm4, %xmm0
-; SSE-NEXT: orps %xmm2, %xmm0
-; SSE-NEXT: movaps %xmm3, %xmm2
-; SSE-NEXT: minps %xmm1, %xmm2
-; SSE-NEXT: cmpunordps %xmm1, %xmm1
-; SSE-NEXT: andps %xmm1, %xmm3
-; SSE-NEXT: andnps %xmm2, %xmm1
-; SSE-NEXT: orps %xmm3, %xmm1
-; SSE-NEXT: retq
+; SSE2-LABEL: test_intrinsic_fmin_v8f32:
+; SSE2: # %bb.0:
+; SSE2-NEXT: movaps %xmm2, %xmm4
+; SSE2-NEXT: minps %xmm0, %xmm4
+; SSE2-NEXT: cmpunordps %xmm0, %xmm0
+; SSE2-NEXT: andps %xmm0, %xmm2
+; SSE2-NEXT: andnps %xmm4, %xmm0
+; SSE2-NEXT: orps %xmm2, %xmm0
+; SSE2-NEXT: movaps %xmm3, %xmm2
+; SSE2-NEXT: minps %xmm1, %xmm2
+; SSE2-NEXT: cmpunordps %xmm1, %xmm1
+; SSE2-NEXT: andps %xmm1, %xmm3
+; SSE2-NEXT: andnps %xmm2, %xmm1
+; SSE2-NEXT: orps %xmm3, %xmm1
+; SSE2-NEXT: retq
+;
+; SSE4-LABEL: test_intrinsic_fmin_v8f32:
+; SSE4: # %bb.0:
+; SSE4-NEXT: movaps %xmm1, %xmm5
+; SSE4-NEXT: movaps %xmm2, %xmm4
+; SSE4-NEXT: minps %xmm0, %xmm4
+; SSE4-NEXT: cmpunordps %xmm0, %xmm0
+; SSE4-NEXT: blendvps %xmm0, %xmm2, %xmm4
+; SSE4-NEXT: movaps %xmm3, %xmm1
+; SSE4-NEXT: minps %xmm5, %xmm1
+; SSE4-NEXT: cmpunordps %xmm5, %xmm5
+; SSE4-NEXT: movaps %xmm5, %xmm0
+; SSE4-NEXT: blendvps %xmm0, %xmm3, %xmm1
+; SSE4-NEXT: movaps %xmm4, %xmm0
+; SSE4-NEXT: retq
;
; AVX-LABEL: test_intrinsic_fmin_v8f32:
; AVX: # %bb.0:
@@ -258,33 +292,60 @@ define <8 x float> @test_intrinsic_fmin_v8f32(<8 x float> %x, <8 x float> %y) {
}
define <16 x float> @test_intrinsic_fmin_v16f32(<16 x float> %x, <16 x float> %y) {
-; SSE-LABEL: test_intrinsic_fmin_v16f32:
-; SSE: # %bb.0:
-; SSE-NEXT: movaps %xmm4, %xmm8
-; SSE-NEXT: minps %xmm0, %xmm8
-; SSE-NEXT: cmpunordps %xmm0, %xmm0
-; SSE-NEXT: andps %xmm0, %xmm4
-; SSE-NEXT: andnps %xmm8, %xmm0
-; SSE-NEXT: orps %xmm4, %xmm0
-; SSE-NEXT: movaps %xmm5, %xmm4
-; SSE-NEXT: minps %xmm1, %xmm4
-; SSE-NEXT: cmpunordps %xmm1, %xmm1
-; SSE-NEXT: andps %xmm1, %xmm5
-; SSE-NEXT: andnps %xmm4, %xmm1
-; SSE-NEXT: orps %xmm5, %xmm1
-; SSE-NEXT: movaps %xmm6, %xmm4
-; SSE-NEXT: minps %xmm2, %xmm4
-; SSE-NEXT: cmpunordps %xmm2, %xmm2
-; SSE-NEXT: andps %xmm2, %xmm6
-; SSE-NEXT: andnps %xmm4, %xmm2
-; SSE-NEXT: orps %xmm6, %xmm2
-; SSE-NEXT: movaps %xmm7, %xmm4
-; SSE-NEXT: minps %xmm3, %xmm4
-; SSE-NEXT: cmpunordps %xmm3, %xmm3
-; SSE-NEXT: andps %xmm3, %xmm7
-; SSE-NEXT: andnps %xmm4, %xmm3
-; SSE-NEXT: orps %xmm7, %xmm3
-; SSE-NEXT: retq
+; SSE2-LABEL: test_intrinsic_fmin_v16f32:
+; SSE2: # %bb.0:
+; SSE2-NEXT: movaps %xmm4, %xmm8
+; SSE2-NEXT: minps %xmm0, %xmm8
+; SSE2-NEXT: cmpunordps %xmm0, %xmm0
+; SSE2-NEXT: andps %xmm0, %xmm4
+; SSE2-NEXT: andnps %xmm8, %xmm0
+; SSE2-NEXT: orps %xmm4, %xmm0
+; SSE2-NEXT: movaps %xmm5, %xmm4
+; SSE2-NEXT: minps %xmm1, %xmm4
+; SSE2-NEXT: cmpunordps %xmm1, %xmm1
+; SSE2-NEXT: andps %xmm1, %xmm5
+; SSE2-NEXT: andnps %xmm4, %xmm1
+; SSE2-NEXT: orps %xmm5, %xmm1
+; SSE2-NEXT: movaps %xmm6, %xmm4
+; SSE2-NEXT: minps %xmm2, %xmm4
+; SSE2-NEXT: cmpunordps %xmm2, %xmm2
+; SSE2-NEXT: andps %xmm2, %xmm6
+; SSE2-NEXT: andnps %xmm4, %xmm2
+; SSE2-NEXT: orps %xmm6, %xmm2
+; SSE2-NEXT: movaps %xmm7, %xmm4
+; SSE2-NEXT: minps %xmm3, %xmm4
+; SSE2-NEXT: cmpunordps %xmm3, %xmm3
+; SSE2-NEXT: andps %xmm3, %xmm7
+; SSE2-NEXT: andnps %xmm4, %xmm3
+; SSE2-NEXT: orps %xmm7, %xmm3
+; SSE2-NEXT: retq
+;
+; SSE4-LABEL: test_intrinsic_fmin_v16f32:
+; SSE4: # %bb.0:
+; SSE4-NEXT: movaps %xmm3, %xmm8
+; SSE4-NEXT: movaps %xmm2, %xmm9
+; SSE4-NEXT: movaps %xmm1, %xmm2
+; SSE4-NEXT: movaps %xmm4, %xmm10
+; SSE4-NEXT: minps %xmm0, %xmm10
+; SSE4-NEXT: cmpunordps %xmm0, %xmm0
+; SSE4-NEXT: blendvps %xmm0, %xmm4, %xmm10
+; SSE4-NEXT: movaps %xmm5, %xmm1
+; SSE4-NEXT: minps %xmm2, %xmm1
+; SSE4-NEXT: cmpunordps %xmm2, %xmm2
+; SSE4-NEXT: movaps %xmm2, %xmm0
+; SSE4-NEXT: blendvps %xmm0, %xmm5, %xmm1
+; SSE4-NEXT: movaps %xmm6, %xmm2
+; SSE4-NEXT: minps %xmm9, %xmm2
+; SSE4-NEXT: cmpunordps %xmm9, %xmm9
+; SSE4-NEXT: movaps %xmm9, %xmm0
+; SSE4-NEXT: blendvps %xmm0, %xmm6, %xmm2
+; SSE4-NEXT: movaps %xmm7, %xmm3
+; SSE4-NEXT: minps %xmm8, %xmm3
+; SSE4-NEXT: cmpunordps %xmm8, %xmm8
+; SSE4-NEXT: movaps %xmm8, %xmm0
+; SSE4-NEXT: blendvps %xmm0, %xmm7, %xmm3
+; SSE4-NEXT: movaps %xmm10, %xmm0
+; SSE4-NEXT: retq
;
; AVX1-LABEL: test_intrinsic_fmin_v16f32:
; AVX1: # %bb.0:
@@ -308,15 +369,24 @@ define <16 x float> @test_intrinsic_fmin_v16f32(<16 x float> %x, <16 x float> %y
}
define <2 x double> @test_intrinsic_fmin_v2f64(<2 x double> %x, <2 x double> %y) {
-; SSE-LABEL: test_intrinsic_fmin_v2f64:
-; SSE: # %bb.0:
-; SSE-NEXT: movapd %xmm1, %xmm2
-; SSE-NEXT: minpd %xmm0, %xmm2
-; SSE-NEXT: cmpunordpd %xmm0, %xmm0
-; SSE-NEXT: andpd %xmm0, %xmm1
-; SSE-NEXT: andnpd %xmm2, %xmm0
-; SSE-NEXT: orpd %xmm1, %xmm0
-; SSE-NEXT: retq
+; SSE2-LABEL: test_intrinsic_fmin_v2f64:
+; SSE2: # %bb.0:
+; SSE2-NEXT: movapd %xmm1, %xmm2
+; SSE2-NEXT: minpd %xmm0, %xmm2
+; SSE2-NEXT: cmpunordpd %xmm0, %xmm0
+; SSE2-NEXT: andpd %xmm0, %xmm1
+; SSE2-NEXT: andnpd %xmm2, %xmm0
+; SSE2-NEXT: orpd %xmm1, %xmm0
+; SSE2-NEXT: retq
+;
+; SSE4-LABEL: test_intrinsic_fmin_v2f64:
+; SSE4: # %bb.0:
+; SSE4-NEXT: movapd %xmm1, %xmm2
+; SSE4-NEXT: minpd %xmm0, %xmm2
+; SSE4-NEXT: cmpunordpd %xmm0, %xmm0
+; SSE4-NEXT: blendvpd %xmm0, %xmm1, %xmm2
+; SSE4-NEXT: movapd %xmm2, %xmm0
+; SSE4-NEXT: retq
;
; AVX-LABEL: test_intrinsic_fmin_v2f64:
; AVX: # %bb.0:
@@ -329,21 +399,36 @@ define <2 x double> @test_intrinsic_fmin_v2f64(<2 x double> %x, <2 x double> %y)
}
define <4 x double> @test_intrinsic_fmin_v4f64(<4 x double> %x, <4 x double> %y) {
-; SSE-LABEL: test_intrinsic_fmin_v4f64:
-; SSE: # %bb.0:
-; SSE-NEXT: movapd %xmm2, %xmm4
-; SSE-NEXT: minpd %xmm0, %xmm4
-; SSE-NEXT: cmpunordpd %xmm0, %xmm0
-; SSE-NEXT: andpd %xmm0, %xmm2
-; SSE-NEXT: andnpd %xmm4, %xmm0
-; SSE-NEXT: orpd %xmm2, %xmm0
-; SSE-NEXT: movapd %xmm3, %xmm2
-; SSE-NEXT: minpd %xmm1, %xmm2
-; SSE-NEXT: cmpunordpd %xmm1, %xmm1
-; SSE-NEXT: andpd %xmm1, %xmm3
-; SSE-NEXT: andnpd %xmm2, %xmm1
-; SSE-NEXT: orpd %xmm3, %xmm1
-; SSE-NEXT: retq
+; SSE2-LABEL: test_intrinsic_fmin_v4f64:
+; SSE2: # %bb.0:
+; SSE2-NEXT: movapd %xmm2, %xmm4
+; SSE2-NEXT: minpd %xmm0, %xmm4
+; SSE2-NEXT: cmpunordpd %xmm0, %xmm0
+; SSE2-NEXT: andpd %xmm0, %xmm2
+; SSE2-NEXT: andnpd %xmm4, %xmm0
+; SSE2-NEXT: orpd %xmm2, %xmm0
+; SSE2-NEXT: movapd %xmm3, %xmm2
+; SSE2-NEXT: minpd %xmm1, %xmm2
+; SSE2-NEXT: cmpunordpd %xmm1, %xmm1
+; SSE2-NEXT: andpd %xmm1, %xmm3
+; SSE2-NEXT: andnpd %xmm2, %xmm1
+; SSE2-NEXT: orpd %xmm3, %xmm1
+; SSE2-NEXT: retq
+;
+; SSE4-LABEL: test_intrinsic_fmin_v4f64:
+; SSE4: # %bb.0:
+; SSE4-NEXT: movapd %xmm1, %xmm5
+; SSE4-NEXT: movapd %xmm2, %xmm4
+; SSE4-NEXT: minpd %xmm0, %xmm4
+; SSE4-NEXT: cmpunordpd %xmm0, %xmm0
+; SSE4-NEXT: blendvpd %xmm0, %xmm2, %xmm4
+; SSE4-NEXT: movapd %xmm3, %xmm1
+; SSE4-NEXT: minpd %xmm5, %xmm1
+; SSE4-NEXT: cmpunordpd %xmm5, %xmm5
+; SSE4-NEXT: movapd %xmm5, %xmm0
+; SSE4-NEXT: blendvpd %xmm0, %xmm3, %xmm1
+; SSE4-NEXT: movapd %xmm4, %xmm0
+; SSE4-NEXT: retq
;
; AVX-LABEL: test_intrinsic_fmin_v4f64:
; AVX: # %bb.0:
@@ -356,33 +441,60 @@ define <4 x double> @test_intrinsic_fmin_v4f64(<4 x double> %x, <4 x double> %y)
}
define <8 x double> @test_intrinsic_fmin_v8f64(<8 x double> %x, <8 x double> %y) {
-; SSE-LABEL: test_intrinsic_fmin_v8f64:
-; SSE: # %bb.0:
-; SSE-NEXT: movapd %xmm4, %xmm8
-; SSE-NEXT: minpd %xmm0, %xmm8
-; SSE-NEXT: cmpunordpd %xmm0, %xmm0
-; SSE-NEXT: andpd %xmm0, %xmm4
-; SSE-NEXT: andnpd %xmm8, %xmm0
-; SSE-NEXT: orpd %xmm4, %xmm0
-; SSE-NEXT: movapd %xmm5, %xmm4
-; SSE-NEXT: minpd %xmm1, %xmm4
-; SSE-NEXT: cmpunordpd %xmm1, %xmm1
-; SSE-NEXT: andpd %xmm1, %xmm5
-; SSE-NEXT: andnpd %xmm4, %xmm1
-; SSE-NEXT: orpd %xmm5, %xmm1
-; SSE-NEXT: movapd %xmm6, %xmm4
-; SSE-NEXT: minpd %xmm2, %xmm4
-; SSE-NEXT: cmpunordpd %xmm2, %xmm2
-; SSE-NEXT: andpd %xmm2, %xmm6
-; SSE-NEXT: andnpd %xmm4, %xmm2
-; SSE-NEXT: orpd %xmm6, %xmm2
-; SSE-NEXT: movapd %xmm7, %xmm4
-; SSE-NEXT: minpd %xmm3, %xmm4
-; SSE-NEXT: cmpunordpd %xmm3, %xmm3
-; SSE-NEXT: andpd %xmm3, %xmm7
-; SSE-NEXT: andnpd %xmm4, %xmm3
-; SSE-NEXT: orpd %xmm7, %xmm3
-; SSE-NEXT: retq
+; SSE2-LABEL: test_intrinsic_fmin_v8f64:
+; SSE2: # %bb.0:
+; SSE2-NEXT: movapd %xmm4, %xmm8
+; SSE2-NEXT: minpd %xmm0, %xmm8
+; SSE2-NEXT: cmpunordpd %xmm0, %xmm0
+; SSE2-NEXT: andpd %xmm0, %xmm4
+; SSE2-NEXT: andnpd %xmm8, %xmm0
+; SSE2-NEXT: orpd %xmm4, %xmm0
+; SSE2-NEXT: movapd %xmm5, %xmm4
+; SSE2-NEXT: minpd %xmm1, %xmm4
+; SSE2-NEXT: cmpunordpd %xmm1, %xmm1
+; SSE2-NEXT: andpd %xmm1, %xmm5
+; SSE2-NEXT: andnpd %xmm4, %xmm1
+; SSE2-NEXT: orpd %xmm5, %xmm1
+; SSE2-NEXT: movapd %xmm6, %xmm4
+; SSE2-NEXT: minpd %xmm2, %xmm4
+; SSE2-NEXT: cmpunordpd %xmm2, %xmm2
+; SSE2-NEXT: andpd %xmm2, %xmm6
+; SSE2-NEXT: andnpd %xmm4, %xmm2
+; SSE2-NEXT: orpd %xmm6, %xmm2
+; SSE2-NEXT: movapd %xmm7, %xmm4
+; SSE2-NEXT: minpd %xmm3, %xmm4
+; SSE2-NEXT: cmpunordpd %xmm3, %xmm3
+; SSE2-NEXT: andpd %xmm3, %xmm7
+; SSE2-NEXT: andnpd %xmm4, %xmm3
+; SSE2-NEXT: orpd %xmm7, %xmm3
+; SSE2-NEXT: retq
+;
+; SSE4-LABEL: test_intrinsic_fmin_v8f64:
+; SSE4: # %bb.0:
+; SSE4-NEXT: movapd %xmm3, %xmm8
+; SSE4-NEXT: movapd %xmm2, %xmm9
+; SSE4-NEXT: movapd %xmm1, %xmm2
+; SSE4-NEXT: movapd %xmm4, %xmm10
+; SSE4-NEXT: minpd %xmm0, %xmm10
+; SSE4-NEXT: cmpunordpd %xmm0, %xmm0
+; SSE4-NEXT: blendvpd %xmm0, %xmm4, %xmm10
+; SSE4-NEXT: movapd %xmm5, %xmm1
+; SSE4-NEXT: minpd %xmm2, %xmm1
+; SSE4-NEXT: cmpunordpd %xmm2, %xmm2
+; SSE4-NEXT: movapd %xmm2, %xmm0
+; SSE4-NEXT: blendvpd %xmm0, %xmm5, %xmm1
+; SSE4-NEXT: movapd %xmm6, %xmm2
+; SSE4-NEXT: minpd %xmm9, %xmm2
+; SSE4-NEXT: cmpunordpd %xmm9, %xmm9
+; SSE4-NEXT: movapd %xmm9, %xmm0
+; SSE4-NEXT: blendvpd %xmm0, %xmm6, %xmm2
+; SSE4-NEXT: movapd %xmm7, %xmm3
+; SSE4-NEXT: minpd %xmm8, %xmm3
+; SSE4-NEXT: cmpunordpd %xmm8, %xmm8
+; SSE4-NEXT: movapd %xmm8, %xmm0
+; SSE4-NEXT: blendvpd %xmm0, %xmm7, %xmm3
+; SSE4-NEXT: movapd %xmm10, %xmm0
+; SSE4-NEXT: retq
;
; AVX1-LABEL: test_intrinsic_fmin_v8f64:
; AVX1: # %bb.0:
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