[PATCH] D75428: [MC][ARM] add implicit immediate form for ldrsbt/ldrht/ldrsht

[Stefan Agner via Phabricator via llvm-commits]

falstaff84 updated this revision to Diff 249249.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75428/new/

https://reviews.llvm.org/D75428

Files:
  llvm/lib/Target/ARM/ARMInstrInfo.td
  llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  llvm/test/MC/ARM/arm-memory-instructions.s


Index: llvm/test/MC/ARM/arm-memory-instructions.s
===================================================================
--- llvm/test/MC/ARM/arm-memory-instructions.s
+++ llvm/test/MC/ARM/arm-memory-instructions.s
@@ -194,11 +194,13 @@
 @------------------------------------------------------------------------------
         ldrht r9, [r7], #128
         ldrht r4, [r3], #-75
+        ldrht r4, [r3]
         ldrht r9, [r7], r2
         ldrht r4, [r3], -r2
 
 @ CHECK: ldrht	r9, [r7], #128          @ encoding: [0xb0,0x98,0xf7,0xe0]
 @ CHECK: ldrht	r4, [r3], #-75          @ encoding: [0xbb,0x44,0x73,0xe0]
+@ CHECK: ldrht	r4, [r3], #0            @ encoding: [0xb0,0x40,0xf3,0xe0]
 @ CHECK: ldrht	r9, [r7], r2            @ encoding: [0xb2,0x90,0xb7,0xe0]
 @ CHECK: ldrht	r4, [r3], -r2           @ encoding: [0xb2,0x40,0x33,0xe0]
 
@@ -244,11 +246,13 @@
 @------------------------------------------------------------------------------
         ldrsbt r5, [r6], #1
         ldrsbt r3, [r8], #-12
+        ldrsbt r5, [r6]
         ldrsbt r8, [r9], r5
         ldrsbt r2, [r1], -r4
 
 @ CHECK: ldrsbt	r5, [r6], #1            @ encoding: [0xd1,0x50,0xf6,0xe0]
 @ CHECK: ldrsbt	r3, [r8], #-12          @ encoding: [0xdc,0x30,0x78,0xe0]
+@ CHECK: ldrsbt	r5, [r6], #0            @ encoding: [0xd0,0x50,0xf6,0xe0]
 @ CHECK: ldrsbt	r8, [r9], r5            @ encoding: [0xd5,0x80,0xb9,0xe0]
 @ CHECK: ldrsbt	r2, [r1], -r4           @ encoding: [0xd4,0x20,0x31,0xe0]
 
@@ -293,11 +297,13 @@
 @------------------------------------------------------------------------------
         ldrsht r5, [r6], #1
         ldrsht r3, [r8], #-12
+        ldrsht r5, [r6]
         ldrsht r8, [r9], r5
         ldrsht r2, [r1], -r4
 
 @ CHECK: ldrsht	r5, [r6], #1            @ encoding: [0xf1,0x50,0xf6,0xe0]
 @ CHECK: ldrsht	r3, [r8], #-12          @ encoding: [0xfc,0x30,0x78,0xe0]
+@ CHECK: ldrsht	r5, [r6], #0            @ encoding: [0xf0,0x50,0xf6,0xe0]
 @ CHECK: ldrsht	r8, [r9], r5            @ encoding: [0xf5,0x80,0xb9,0xe0]
 @ CHECK: ldrsht	r2, [r1], -r4           @ encoding: [0xf4,0x20,0x31,0xe0]
 
Index: llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
===================================================================
--- llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -8546,6 +8546,26 @@
     Inst = TmpInst;
     return true;
   }
+  // Alias for 'ldr{sb,h,sh}t Rt, [Rn] {, #imm}' for ommitted immediate.
+  case ARM::LDRSBTii:
+  case ARM::LDRHTii:
+  case ARM::LDRSHTii: {
+    MCInst TmpInst;
+
+    if (Inst.getOpcode() == ARM::LDRSBTii)
+      TmpInst.setOpcode(ARM::LDRSBTi);
+    else if (Inst.getOpcode() == ARM::LDRHTii)
+      TmpInst.setOpcode(ARM::LDRHTi);
+    else if (Inst.getOpcode() == ARM::LDRSHTii)
+      TmpInst.setOpcode(ARM::LDRSHTi);
+    TmpInst.addOperand(Inst.getOperand(0));
+    TmpInst.addOperand(Inst.getOperand(1));
+    TmpInst.addOperand(Inst.getOperand(1));
+    TmpInst.addOperand(MCOperand::createImm(256));
+    TmpInst.addOperand(Inst.getOperand(2));
+    Inst = TmpInst;
+    return true;
+  }
   // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
   case ARM::STRT_POST:
   case ARM::STRBT_POST: {
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrInfo.td
+++ llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -2967,6 +2967,9 @@
     let Inst{3-0} = Rm{3-0};
     let DecoderMethod = "DecodeLDR";
   }
+
+  def ii : ARMAsmPseudo<!strconcat(opc, "${p} $Rt, $addr"),
+                        (ins addr_offset_none:$addr, pred:$p), (outs GPR:$Rt)>;
 }
 
 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;


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