[llvm] c7b2e7f - [AMDGPU] Fix scheduling info for terminator SALU instructions

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2020-03-09T21:39:52Z
New Revision: c7b2e7f52742add7444fba2c04e4fa60b3ea4813

URL: https://github.com/llvm/llvm-project/commit/c7b2e7f52742add7444fba2c04e4fa60b3ea4813
DIFF: https://github.com/llvm/llvm-project/commit/c7b2e7f52742add7444fba2c04e4fa60b3ea4813.diff

LOG: [AMDGPU] Fix scheduling info for terminator SALU instructions

Summary:
Instruction variants like S_MOV_B32_term should have the same SchedRW
class as the base instruction, S_MOV_B32. This probably doesn't make any
difference in practice because as terminators, they'll always be
scheduled at the end of a basic block, but it's simply more correct than
giving them all the default SchedRW class of Write32Bit, which implies a
VALU operation.

Reviewers: rampitec, arsenm, nhaehnle

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D75860

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIInstructions.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 380b6dd7a6e7..c1cace273f05 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -230,6 +230,7 @@ class WrapTerminatorInst<SOP_Pseudo base_inst> : SPseudoInstSI<
   let hasSideEffects = base_inst.hasSideEffects;
   let UseNamedOperandTable = base_inst.UseNamedOperandTable;
   let CodeSize = base_inst.CodeSize;
+  let SchedRW = base_inst.SchedRW;
 }
 
 let WaveSizePredicate = isWave64 in {