[PATCH] D75857: [AMDGPU] Fix using physical registers in vector instructions

Matt Arsenault via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Mar 9 10:14:00 PDT 2020

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arsenm added a comment.

Need test and I would expect a physical register to never appear in this context


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D75857/new/

https://reviews.llvm.org/D75857

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