[PATCH] D75064: [AArch64][SVE] Add support for DestructiveBinaryImm DestructiveInstType

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:1107
 
-  defm ASR_ZPmZ  : sve_int_bin_pred_shift<0b000, "asr", int_aarch64_sve_asr>;
-  defm LSR_ZPmZ  : sve_int_bin_pred_shift<0b001, "lsr", int_aarch64_sve_lsr>;
-  defm LSL_ZPmZ  : sve_int_bin_pred_shift<0b011, "lsl", int_aarch64_sve_lsl>;
-  defm ASRR_ZPmZ : sve_int_bin_pred_shift<0b100, "asrr", null_frag>;
-  defm LSRR_ZPmZ : sve_int_bin_pred_shift<0b101, "lsrr", null_frag>;
-  defm LSLR_ZPmZ : sve_int_bin_pred_shift<0b111, "lslr", null_frag>;
+  defm ASR_ZPZZ  : sve_int_bin_pred_zx<int_aarch64_sve_asr>;
+  defm LSR_ZPZZ  : sve_int_bin_pred_zx<int_aarch64_sve_lsr>;
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The _zx suggests it covers the merging with undef case as well. Are those patterns you plan to add in this patch?


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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:4746
                                             SDPatternOperator op = null_frag> {
-  def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>;
-  def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> {
-    let Inst{8} = imm{3};
-  }
-  def _S : sve_int_bin_pred_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> {
-    let Inst{9-8} = imm{4-3};
-  }
-  def _D : sve_int_bin_pred_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> {
-    let Inst{22}  = imm{5};
-    let Inst{9-8} = imm{4-3};
+  let DestructiveInstType = DestructiveBinaryImm in {
+    def _B : SVEPseudo2Instr<Ps # _B, 1>,
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I think this change isn't needed anymore if `let DestructiveInstType = DestructiveBinaryImm` is added to line 4702.


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  https://reviews.llvm.org/D75064/new/

https://reviews.llvm.org/D75064