[PATCH] D75347: [MC][ELF][ARM] Add relocations for some ARM pc-relative fixups.

[Peter Smith via Phabricator via llvm-commits]

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================
Comment at: llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp:140
       }
+    case ARM::fixup_arm_adr_pcrel_12:
+      return ELF::R_ARM_ALU_PC_G0;
----------------
MaskRay wrote:
> From the fixup name it is hard to predicate the name of the relocation type. Does anyone know why?
Apologies for the delay in responding. I missed the notification in the inbox. I don't have a particularly good answer, my guess is that there is a mix of ELF and MachO terminology from the assembler, with more of a slant towards MachO than ELF. The 12 will refer to the number of bits in the immediate.

The G0 is short for Group 0. The relocations while too short ranged to be useful on their own can be used in groups to load much more useful constants. The intention is to write something like the Arm PLT entry. In LLD we hard code the masks but in principle they can be calculated by relocations.
```
ADD ip, pc, #-8:PC_OFFSET_27_20: X ; R_ARM_ALU_PC_G0_NC(X)
ADD ip, ip, #-4:PC_OFFSET_19_12: X ; R_ARM_ALU_PC_G1_NC(X)
LDR pc, [ip, #0:PC_OFFSET_11_0: X]! ; R_ARM_LDR_PC_G2(X)
```
The G0 and G1 each take 8 bytes of the offset to X then LDR uses the bottom 12 for the offset. For example:
```
ip = pc + (X & 0x0ff00000)
ip = ip + (X & 0x000ff000)
pc = [ip + 0x00000fff]
```



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https://reviews.llvm.org/D75347