[PATCH] D75504: [AMDGPU] moving vcc branch optimization into peephole

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp:1017
   addPass(&SIRemoveShortExecBranchesID);
+  addPass(&PeepholeOptimizerID);
   addPass(&SIInsertSkipsPassID);
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cdevadas wrote:
> arsenm wrote:
> > Should not need an extra run of this
> The peephole is invoked earlier during SSAOptimization. It is required here to optimize the pattern introduced later. The lit test multilevel-break.ll has a similar opportunity in function multi_if_break_loop. 
Where is the pattern introduced? Does this ever trigger in the initial run?


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Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:2182
+
+    unsigned SReg = AMDGPU::NoRegister;
+    if (Op2.isReg()) {
----------------
cdevadas wrote:
> arsenm wrote:
> > Register, and initialization isn't needed
> Are you saying the initialization is not required? 
> SReg is not defined in all control-flows later.
If you use Register instead of unsigned, it default initializes to NoRegister/0


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75504/new/

https://reviews.llvm.org/D75504