[PATCH] D75667: [ARM][MVE] Enable *SHRN* for tail predication

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Not sure. I think they are just register types at the instruction level. I thought that was why we excluded many instructions (like vmull and vshrn), because they all change the types, and that changing of the types probably means that the tail predication might not be valid.

>From IR I think that would be <8 x i16> sext to <8 x i32>, so the number of lanes would be the same, but the types (and lanes they are computed in) changes.

PS. I noticed VFMA.f32 isn't marked as valid. I think that's one that should certainly be OK.


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https://reviews.llvm.org/D75667