[PATCH] D75729: [RISCV] Select +0.0 immediate using fcvt.{d, s}.{x, w} fN, x0

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 created this revision.
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rogfer01 added a parent revision: D75728: [NFC][RISCV] Test for 0.0 fp immediate.

The RISC-V ISA Spec, in the chapter about the F extension, says

> A floating-point register can be initialized to floating-point positive zero using `FCVT.S.W rd, x0`, which will never set any exception flags.

The spec doesn't have a similar wording for the D extension but I presume a similar behaviour is to be expected for `FCVT.D.L`. Similarly for `FCVT.S.L` and `FCVT.D.W`


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D75729

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/test/CodeGen/RISCV/double-arith.ll
  llvm/test/CodeGen/RISCV/float-arith.ll
  llvm/test/CodeGen/RISCV/float-br-fcmp.ll
  llvm/test/CodeGen/RISCV/fp-imm.ll

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