[PATCH] D75624: [DAG] Combine fshl/fshr(load1,load0,c) if we have consecutive loads

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon updated this revision to Diff 248437.
RKSimon added a comment.

Add allowsMemoryAccess check to ensure alignment is legal and fast


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75624/new/

https://reviews.llvm.org/D75624

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/X86/fshl.ll
  llvm/test/CodeGen/X86/fshr.ll

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