[PATCH] D75344: [PowerPC] Exploit VSX neg, abs and nabs instruction for f32

[qshanz via Phabricator via llvm-commits]

steven.zhang added inline comments.


================
Comment at: llvm/test/CodeGen/PowerPC/fma.ll:130
+; CHECK-VSX: fmsubs
+; CHECK-VSX: xsnegdp
 ; CHECK-VSX-NEXT: blr
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qiucf wrote:
> I know here looks like a regression. But I'm drafting another patch to disable `nmsub` instruction when no `nsz` flag set. So the pattern will be removed from td file and we can get `xsnmsubadp` naturally.
So, could you please post that patch here as the parent revision of this one, then update the patch, so that, we could have a clear picture.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D75344/new/

https://reviews.llvm.org/D75344