[PATCH] D75624: [DAG] Combine fshl/fshr(load1,load0,c) if we have consecutive loads

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon marked an inline comment as done.
RKSimon added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:8271
+          (LHS->hasOneUse() || RHS->hasOneUse()) && ISD::isNON_EXTLoad(RHS)) {
+        if (DAG.areNonVolatileConsecutiveLoads(LHS, RHS, BitWidth / 8, 1)) {
+          SDLoc DL(RHS);
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efriedma wrote:
> Do you need to check whether unaligned loads are supported for the given type?
Thanks, I'll add an TLI.allowsMemoryAccess check - speaking of which, a lot of combines seem to use a getABITypeAlignment check which seems like overkill to me?


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https://reviews.llvm.org/D75624