[llvm] 587feec - [ARM] Change all tests from "thumbv8.1-m.main" to "thumbv8.1m.main". NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 4 05:47:55 PST 2020
Author: David Green
Date: 2020-03-04T13:47:35Z
New Revision: 587feec07e3e8028ba40018c5316b5bf353fee3f
URL: https://github.com/llvm/llvm-project/commit/587feec07e3e8028ba40018c5316b5bf353fee3f
DIFF: https://github.com/llvm/llvm-project/commit/587feec07e3e8028ba40018c5316b5bf353fee3f.diff
LOG: [ARM] Change all tests from "thumbv8.1-m.main" to "thumbv8.1m.main". NFC
Added:
Modified:
llvm/test/Analysis/CostModel/ARM/arith.ll
llvm/test/Analysis/CostModel/ARM/cast.ll
llvm/test/Analysis/CostModel/ARM/divrem.ll
llvm/test/Analysis/CostModel/ARM/fparith.ll
llvm/test/Analysis/CostModel/ARM/gep.ll
llvm/test/Analysis/CostModel/ARM/load_store.ll
llvm/test/Analysis/CostModel/ARM/mve-gather-scatter-cost.ll
llvm/test/Analysis/CostModel/ARM/select.ll
llvm/test/Analysis/CostModel/ARM/shuffle.ll
llvm/test/CodeGen/ARM/shift_parts.ll
llvm/test/CodeGen/Thumb2/mve-vpt-nots.mir
llvm/test/Transforms/LoopVectorize/ARM/mve-interleaved-cost.ll
llvm/test/Transforms/LoopVectorize/ARM/mve-maskedldst.ll
Removed:
################################################################################
diff --git a/llvm/test/Analysis/CostModel/ARM/arith.ll b/llvm/test/Analysis/CostModel/ARM/arith.ll
index ad9a3d5a0791..4e9de7a122ce 100644
--- a/llvm/test/Analysis/CostModel/ARM/arith.ll
+++ b/llvm/test/Analysis/CostModel/ARM/arith.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
-; RUN: opt -cost-model -analyze -mtriple=thumbv8.1-m.main-none-eabi -mattr=+mve,+mve1beat < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE1
-; RUN: opt -cost-model -analyze -mtriple=thumbv8.1-m.main-none-eabi -mattr=+mve < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE2
-; RUN: opt -cost-model -analyze -mtriple=thumbv8.1-m.main-none-eabi -mattr=+mve,+mve4beat < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE4
+; RUN: opt -cost-model -analyze -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve,+mve1beat < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE1
+; RUN: opt -cost-model -analyze -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE2
+; RUN: opt -cost-model -analyze -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve,+mve4beat < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE4
define void @i8() {
; CHECK-LABEL: 'i8'
diff --git a/llvm/test/Analysis/CostModel/ARM/cast.ll b/llvm/test/Analysis/CostModel/ARM/cast.ll
index 0b068b5e0e9b..d7592124f886 100644
--- a/llvm/test/Analysis/CostModel/ARM/cast.ll
+++ b/llvm/test/Analysis/CostModel/ARM/cast.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=cortex-a9 | FileCheck %s --check-prefix=CHECK-NEON
-; RUN: opt -cost-model -analyze -mtriple=thumbv8.1-m.main-none-eabi -mattr=+mve.fp < %s | FileCheck %s --check-prefix=CHECK-MVE
+; RUN: opt -cost-model -analyze -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp < %s | FileCheck %s --check-prefix=CHECK-MVE
define i32 @casts() {
; CHECK-NEON-LABEL: 'casts'
diff --git a/llvm/test/Analysis/CostModel/ARM/divrem.ll b/llvm/test/Analysis/CostModel/ARM/divrem.ll
index d20fcb52256b..259981a7dfee 100644
--- a/llvm/test/Analysis/CostModel/ARM/divrem.ll
+++ b/llvm/test/Analysis/CostModel/ARM/divrem.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=cortex-a9 | FileCheck %s --check-prefix=CHECK-NEON
-; RUN: opt -cost-model -analyze -mtriple=thumbv8.1-m.main-none-eabi -mattr=+mve.fp < %s | FileCheck %s --check-prefix=CHECK-MVE
+; RUN: opt -cost-model -analyze -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp < %s | FileCheck %s --check-prefix=CHECK-MVE
define void @i8() {
; CHECK-NEON-LABEL: 'i8'
@@ -117,12 +117,12 @@ define void @i64() {
; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; CHECK-MVE-LABEL: 'i64'
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = sdiv i64 undef, undef
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = udiv i64 undef, undef
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = sdiv i64 undef, undef
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %2 = udiv i64 undef, undef
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = srem i64 undef, undef
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = urem i64 undef, undef
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %5 = sdiv i64 undef, 2
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %6 = udiv i64 undef, 2
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %5 = sdiv i64 undef, 2
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %6 = udiv i64 undef, 2
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = srem i64 undef, 2
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = urem i64 undef, 2
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
@@ -399,20 +399,20 @@ define void @vi64() {
; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; CHECK-MVE-LABEL: 'vi64'
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %t1 = sdiv <2 x i64> undef, undef
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %t2 = udiv <2 x i64> undef, undef
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %t1 = sdiv <2 x i64> undef, undef
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %t2 = udiv <2 x i64> undef, undef
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %t3 = srem <2 x i64> undef, undef
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %t4 = urem <2 x i64> undef, undef
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %f1 = sdiv <4 x i64> undef, undef
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %f2 = udiv <4 x i64> undef, undef
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %f1 = sdiv <4 x i64> undef, undef
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %f2 = udiv <4 x i64> undef, undef
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %f3 = srem <4 x i64> undef, undef
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %f4 = urem <4 x i64> undef, undef
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 72 for instruction: %e1 = sdiv <8 x i64> undef, undef
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 72 for instruction: %e2 = udiv <8 x i64> undef, undef
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %e1 = sdiv <8 x i64> undef, undef
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %e2 = udiv <8 x i64> undef, undef
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 72 for instruction: %e3 = srem <8 x i64> undef, undef
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 72 for instruction: %e4 = urem <8 x i64> undef, undef
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 272 for instruction: %s1 = sdiv <16 x i64> undef, undef
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 272 for instruction: %s2 = udiv <16 x i64> undef, undef
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 288 for instruction: %s1 = sdiv <16 x i64> undef, undef
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 288 for instruction: %s2 = udiv <16 x i64> undef, undef
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 272 for instruction: %s3 = srem <16 x i64> undef, undef
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 272 for instruction: %s4 = urem <16 x i64> undef, undef
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
@@ -715,20 +715,20 @@ define void @vi64_2() {
; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; CHECK-MVE-LABEL: 'vi64_2'
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %t1 = sdiv <2 x i64> undef, <i64 2, i64 2>
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %t2 = udiv <2 x i64> undef, <i64 2, i64 2>
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %t1 = sdiv <2 x i64> undef, <i64 2, i64 2>
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %t2 = udiv <2 x i64> undef, <i64 2, i64 2>
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %t3 = srem <2 x i64> undef, <i64 2, i64 2>
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %t4 = urem <2 x i64> undef, <i64 2, i64 2>
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %f1 = sdiv <4 x i64> undef, <i64 2, i64 2, i64 2, i64 2>
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %f2 = udiv <4 x i64> undef, <i64 2, i64 2, i64 2, i64 2>
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %f1 = sdiv <4 x i64> undef, <i64 2, i64 2, i64 2, i64 2>
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %f2 = udiv <4 x i64> undef, <i64 2, i64 2, i64 2, i64 2>
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %f3 = srem <4 x i64> undef, <i64 2, i64 2, i64 2, i64 2>
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %f4 = urem <4 x i64> undef, <i64 2, i64 2, i64 2, i64 2>
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 72 for instruction: %e1 = sdiv <8 x i64> undef, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 72 for instruction: %e2 = udiv <8 x i64> undef, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %e1 = sdiv <8 x i64> undef, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %e2 = udiv <8 x i64> undef, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 72 for instruction: %e3 = srem <8 x i64> undef, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 72 for instruction: %e4 = urem <8 x i64> undef, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 272 for instruction: %s1 = sdiv <16 x i64> undef, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 272 for instruction: %s2 = udiv <16 x i64> undef, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 288 for instruction: %s1 = sdiv <16 x i64> undef, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 288 for instruction: %s2 = udiv <16 x i64> undef, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 272 for instruction: %s3 = srem <16 x i64> undef, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 272 for instruction: %s4 = urem <16 x i64> undef, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
diff --git a/llvm/test/Analysis/CostModel/ARM/fparith.ll b/llvm/test/Analysis/CostModel/ARM/fparith.ll
index bc2cd104aae6..cb3d66edfa20 100644
--- a/llvm/test/Analysis/CostModel/ARM/fparith.ll
+++ b/llvm/test/Analysis/CostModel/ARM/fparith.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
-; RUN: opt -cost-model -analyze -mtriple=thumbv8.1-m.main-none-eabi -mattr=+mve < %s | FileCheck %s --check-prefix=CHECK-MVE
-; RUN: opt -cost-model -analyze -mtriple=thumbv8.1-m.main-none-eabi -mattr=+mve.fp < %s | FileCheck %s --check-prefix=CHECK-MVEFP
+; RUN: opt -cost-model -analyze -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve < %s | FileCheck %s --check-prefix=CHECK-MVE
+; RUN: opt -cost-model -analyze -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp < %s | FileCheck %s --check-prefix=CHECK-MVEFP
define void @f32() {
; CHECK-MVE-LABEL: 'f32'
diff --git a/llvm/test/Analysis/CostModel/ARM/gep.ll b/llvm/test/Analysis/CostModel/ARM/gep.ll
index a84264b62073..97cf03f25ae0 100644
--- a/llvm/test/Analysis/CostModel/ARM/gep.ll
+++ b/llvm/test/Analysis/CostModel/ARM/gep.ll
@@ -2,8 +2,8 @@
; RUN: opt -cost-model -analyze -mtriple=thumbv6m-none-eabi < %s | FileCheck %s --check-prefix=CHECK-V6M
; RUN: opt -cost-model -analyze -mtriple=thumbv7m-none-eabi -mcpu=cortex-m3 < %s | FileCheck %s --check-prefix=CHECK-V7M --check-prefix=CHECK-V7M-NOFP
; RUN: opt -cost-model -analyze -mtriple=thumbv7m-none-eabi -mcpu=cortex-m4 < %s | FileCheck %s --check-prefix=CHECK-V7M --check-prefix=CHECK-V7M-FP
-; RUN: opt -cost-model -analyze -mtriple=thumbv8.1-m.main-none-eabi -mattr=+mve < %s | FileCheck %s --check-prefix=CHECK-V7M --check-prefix=CHECK-MVE
-; RUN: opt -cost-model -analyze -mtriple=thumbv8.1-m.main-none-eabi -mattr=+mve.fp < %s | FileCheck %s --check-prefix=CHECK-V7M --check-prefix=CHECK-MVEFP
+; RUN: opt -cost-model -analyze -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve < %s | FileCheck %s --check-prefix=CHECK-V7M --check-prefix=CHECK-MVE
+; RUN: opt -cost-model -analyze -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp < %s | FileCheck %s --check-prefix=CHECK-V7M --check-prefix=CHECK-MVEFP
; RUN: opt -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift < %s | FileCheck %s --check-prefix=CHECK-T32
; RUN: opt -cost-model -analyze -mtriple=arm-none-eabi -mcpu=cortex-a53 < %s | FileCheck %s --check-prefix=CHECK-A32
diff --git a/llvm/test/Analysis/CostModel/ARM/load_store.ll b/llvm/test/Analysis/CostModel/ARM/load_store.ll
index 89b18d90f064..0703f1535dc0 100644
--- a/llvm/test/Analysis/CostModel/ARM/load_store.ll
+++ b/llvm/test/Analysis/CostModel/ARM/load_store.ll
@@ -2,7 +2,7 @@
; RUN: opt -cost-model -analyze -mtriple=thumbv6m-none-eabi < %s | FileCheck %s --check-prefix=CHECK-NOVEC
; RUN: opt -cost-model -analyze -mtriple=thumbv7m-none-eabi -mcpu=cortex-m3 < %s | FileCheck %s --check-prefix=CHECK-NOVEC
; RUN: opt -cost-model -analyze -mtriple=thumbv7m-none-eabi -mcpu=cortex-m4 < %s | FileCheck %s --check-prefix=CHECK-FP
-; RUN: opt -cost-model -analyze -mtriple=thumbv8.1-m.main-none-eabi -mattr=+mve < %s | FileCheck %s --check-prefix=CHECK-MVE
+; RUN: opt -cost-model -analyze -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve < %s | FileCheck %s --check-prefix=CHECK-MVE
; RUN: opt -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift < %s | FileCheck %s --check-prefix=CHECK-NEON
; RUN: opt -cost-model -analyze -mtriple=arm-none-eabi -mcpu=cortex-a53 < %s | FileCheck %s --check-prefix=CHECK-NEON
diff --git a/llvm/test/Analysis/CostModel/ARM/mve-gather-scatter-cost.ll b/llvm/test/Analysis/CostModel/ARM/mve-gather-scatter-cost.ll
index 6fd096de2169..0f28d435b5ca 100644
--- a/llvm/test/Analysis/CostModel/ARM/mve-gather-scatter-cost.ll
+++ b/llvm/test/Analysis/CostModel/ARM/mve-gather-scatter-cost.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
-; RUN: opt < %s -S -mtriple=thumbv8.1-m.main-none-eabi -mattr=+mve.fp -cost-model -analyze -enable-arm-maskedgatscat | FileCheck %s
+; RUN: opt < %s -S -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp -cost-model -analyze -enable-arm-maskedgatscat | FileCheck %s
define i32 @masked_gather() {
; CHECK-LABEL: 'masked_gather'
diff --git a/llvm/test/Analysis/CostModel/ARM/select.ll b/llvm/test/Analysis/CostModel/ARM/select.ll
index 4821438e8ad2..c514581f8602 100644
--- a/llvm/test/Analysis/CostModel/ARM/select.ll
+++ b/llvm/test/Analysis/CostModel/ARM/select.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
-; RUN: opt < %s -cost-model -analyze -mtriple=thumbv8.1-m.main-none-eabi -mattr=+mve.fp | FileCheck %s --check-prefix=CHECK-MVE
+; RUN: opt < %s -cost-model -analyze -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp | FileCheck %s --check-prefix=CHECK-MVE
; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift | FileCheck %s --check-prefix=CHECK-NEON
define void @casts() {
diff --git a/llvm/test/Analysis/CostModel/ARM/shuffle.ll b/llvm/test/Analysis/CostModel/ARM/shuffle.ll
index ce2098653c94..5d9f698f1e5a 100644
--- a/llvm/test/Analysis/CostModel/ARM/shuffle.ll
+++ b/llvm/test/Analysis/CostModel/ARM/shuffle.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
-; RUN: opt < %s -cost-model -analyze -mtriple=thumbv8.1-m.main-none-eabi -mattr=+mve.fp | FileCheck %s --check-prefix=CHECK-MVE
+; RUN: opt < %s -cost-model -analyze -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp | FileCheck %s --check-prefix=CHECK-MVE
; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift | FileCheck %s --check-prefix=CHECK-NEON
define void @broadcast() {
diff --git a/llvm/test/CodeGen/ARM/shift_parts.ll b/llvm/test/CodeGen/ARM/shift_parts.ll
index 9bc77d585bf9..bb429edc623e 100644
--- a/llvm/test/CodeGen/ARM/shift_parts.ll
+++ b/llvm/test/CodeGen/ARM/shift_parts.ll
@@ -1,5 +1,6 @@
-; RUN: llc --verify-machineinstrs -mtriple=thumbv8.1-m.main-none-eabi -mattr=+mve %s -o - | FileCheck %s -check-prefix=CHECK --check-prefix=CHECK-MVE
-; RUN: llc --verify-machineinstrs -mtriple=thumbv8.1-m.main-none-eabi %s -o - | FileCheck %s -check-prefix=CHECK --check-prefix=CHECK-NON-MVE
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --verify-machineinstrs -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve %s -o - | FileCheck %s -check-prefix=CHECK --check-prefix=CHECK-MVE
+; RUN: llc --verify-machineinstrs -mtriple=thumbv8.1m.main-none-eabi %s -o - | FileCheck %s -check-prefix=CHECK --check-prefix=CHECK-NON-MVE
define i64 @shift_left_reg(i64 %x, i64 %y) {
; CHECK-MVE-LABEL: shift_left_reg:
@@ -9,12 +10,17 @@ define i64 @shift_left_reg(i64 %x, i64 %y) {
;
; CHECK-NON-MVE-LABEL: shift_left_reg:
; CHECK-NON-MVE: @ %bb.0: @ %entry
-; CHECK-NON-MVE-NEXT: .save {r7, lr}
-; CHECK-NON-MVE-NEXT: push {r7, lr}
-; CHECK-NON-MVE-NEXT: bl __aeabi_llsl
-; CHECK-NON-MVE-NEXT: pop {r7}
-; CHECK-NON-MVE-NEXT: pop {r2}
-; CHECK-NON-MVE-NEXT: bx r2
+; CHECK-NON-MVE-NEXT: rsb.w r3, r2, #32
+; CHECK-NON-MVE-NEXT: lsls r1, r2
+; CHECK-NON-MVE-NEXT: lsr.w r3, r0, r3
+; CHECK-NON-MVE-NEXT: orrs r1, r3
+; CHECK-NON-MVE-NEXT: subs.w r3, r2, #32
+; CHECK-NON-MVE-NEXT: it pl
+; CHECK-NON-MVE-NEXT: lslpl.w r1, r0, r3
+; CHECK-NON-MVE-NEXT: lsl.w r0, r0, r2
+; CHECK-NON-MVE-NEXT: it pl
+; CHECK-NON-MVE-NEXT: movpl r0, #0
+; CHECK-NON-MVE-NEXT: bx lr
entry:
%shl = shl i64 %x, %y
ret i64 %shl
@@ -28,9 +34,8 @@ define i64 @shift_left_imm(i64 %x) {
;
; CHECK-NON-MVE-LABEL: shift_left_imm:
; CHECK-NON-MVE: @ %bb.0: @ %entry
-; CHECK-NON-MVE-NEXT: lsrs r2, r0, #29
; CHECK-NON-MVE-NEXT: lsls r1, r1, #3
-; CHECK-NON-MVE-NEXT: adds r1, r1, r2
+; CHECK-NON-MVE-NEXT: orr.w r1, r1, r0, lsr #29
; CHECK-NON-MVE-NEXT: lsls r0, r0, #3
; CHECK-NON-MVE-NEXT: bx lr
entry:
@@ -50,17 +55,11 @@ entry:
}
define i64 @shift_left_imm_big2(i64 %x) {
-; CHECK-MVE-LABEL: shift_left_imm_big2:
-; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: mov r1, r0
-; CHECK-MVE-NEXT: movs r0, #0
-; CHECK-MVE-NEXT: bx lr
-;
-; CHECK-NON-MVE-LABEL: shift_left_imm_big2:
-; CHECK-NON-MVE: @ %bb.0: @ %entry
-; CHECK-NON-MVE-NEXT: movs r1, r0
-; CHECK-NON-MVE-NEXT: movs r0, #0
-; CHECK-NON-MVE-NEXT: bx lr
+; CHECK-LABEL: shift_left_imm_big2:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: mov r1, r0
+; CHECK-NEXT: movs r0, #0
+; CHECK-NEXT: bx lr
entry:
%shl = shl i64 %x, 32
ret i64 %shl
@@ -86,12 +85,17 @@ define i64 @shift_right_reg(i64 %x, i64 %y) {
;
; CHECK-NON-MVE-LABEL: shift_right_reg:
; CHECK-NON-MVE: @ %bb.0: @ %entry
-; CHECK-NON-MVE-NEXT: .save {r7, lr}
-; CHECK-NON-MVE-NEXT: push {r7, lr}
-; CHECK-NON-MVE-NEXT: bl __aeabi_llsr
-; CHECK-NON-MVE-NEXT: pop {r7}
-; CHECK-NON-MVE-NEXT: pop {r2}
-; CHECK-NON-MVE-NEXT: bx r2
+; CHECK-NON-MVE-NEXT: rsb.w r3, r2, #32
+; CHECK-NON-MVE-NEXT: lsrs r0, r2
+; CHECK-NON-MVE-NEXT: lsl.w r3, r1, r3
+; CHECK-NON-MVE-NEXT: orrs r0, r3
+; CHECK-NON-MVE-NEXT: subs.w r3, r2, #32
+; CHECK-NON-MVE-NEXT: it pl
+; CHECK-NON-MVE-NEXT: lsrpl.w r0, r1, r3
+; CHECK-NON-MVE-NEXT: lsr.w r1, r1, r2
+; CHECK-NON-MVE-NEXT: it pl
+; CHECK-NON-MVE-NEXT: movpl r1, #0
+; CHECK-NON-MVE-NEXT: bx lr
entry:
%shr = lshr i64 %x, %y
ret i64 %shr
@@ -105,9 +109,8 @@ define i64 @shift_right_imm(i64 %x) {
;
; CHECK-NON-MVE-LABEL: shift_right_imm:
; CHECK-NON-MVE: @ %bb.0: @ %entry
-; CHECK-NON-MVE-NEXT: lsls r2, r1, #29
; CHECK-NON-MVE-NEXT: lsrs r0, r0, #3
-; CHECK-NON-MVE-NEXT: adds r0, r0, r2
+; CHECK-NON-MVE-NEXT: orr.w r0, r0, r1, lsl #29
; CHECK-NON-MVE-NEXT: lsrs r1, r1, #3
; CHECK-NON-MVE-NEXT: bx lr
entry:
@@ -127,17 +130,11 @@ entry:
}
define i64 @shift_right_imm_big2(i64 %x) {
-; CHECK-MVE-LABEL: shift_right_imm_big2:
-; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: mov r0, r1
-; CHECK-MVE-NEXT: movs r1, #0
-; CHECK-MVE-NEXT: bx lr
-;
-; CHECK-NON-MVE-LABEL: shift_right_imm_big2:
-; CHECK-NON-MVE: @ %bb.0: @ %entry
-; CHECK-NON-MVE-NEXT: movs r0, r1
-; CHECK-NON-MVE-NEXT: movs r1, #0
-; CHECK-NON-MVE-NEXT: bx lr
+; CHECK-LABEL: shift_right_imm_big2:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: mov r0, r1
+; CHECK-NEXT: movs r1, #0
+; CHECK-NEXT: bx lr
entry:
%shr = lshr i64 %x, 32
ret i64 %shr
@@ -162,12 +159,18 @@ define i64 @shift_arithmetic_right_reg(i64 %x, i64 %y) {
;
; CHECK-NON-MVE-LABEL: shift_arithmetic_right_reg:
; CHECK-NON-MVE: @ %bb.0: @ %entry
-; CHECK-NON-MVE-NEXT: .save {r7, lr}
-; CHECK-NON-MVE-NEXT: push {r7, lr}
-; CHECK-NON-MVE-NEXT: bl __aeabi_lasr
-; CHECK-NON-MVE-NEXT: pop {r7}
-; CHECK-NON-MVE-NEXT: pop {r2}
-; CHECK-NON-MVE-NEXT: bx r2
+; CHECK-NON-MVE-NEXT: rsb.w r3, r2, #32
+; CHECK-NON-MVE-NEXT: lsrs r0, r2
+; CHECK-NON-MVE-NEXT: lsl.w r3, r1, r3
+; CHECK-NON-MVE-NEXT: orrs r0, r3
+; CHECK-NON-MVE-NEXT: subs.w r3, r2, #32
+; CHECK-NON-MVE-NEXT: asr.w r2, r1, r2
+; CHECK-NON-MVE-NEXT: it pl
+; CHECK-NON-MVE-NEXT: asrpl.w r0, r1, r3
+; CHECK-NON-MVE-NEXT: it pl
+; CHECK-NON-MVE-NEXT: asrpl r2, r1, #31
+; CHECK-NON-MVE-NEXT: mov r1, r2
+; CHECK-NON-MVE-NEXT: bx lr
entry:
%shr = ashr i64 %x, %y
ret i64 %shr
@@ -181,9 +184,8 @@ define i64 @shift_arithmetic_right_imm(i64 %x) {
;
; CHECK-NON-MVE-LABEL: shift_arithmetic_right_imm:
; CHECK-NON-MVE: @ %bb.0: @ %entry
-; CHECK-NON-MVE-NEXT: lsls r2, r1, #29
; CHECK-NON-MVE-NEXT: lsrs r0, r0, #3
-; CHECK-NON-MVE-NEXT: adds r0, r0, r2
+; CHECK-NON-MVE-NEXT: orr.w r0, r0, r1, lsl #29
; CHECK-NON-MVE-NEXT: asrs r1, r1, #3
; CHECK-NON-MVE-NEXT: bx lr
entry:
@@ -206,12 +208,10 @@ define arm_aapcs_vfpcc void @fn1(%struct.bar* nocapture %a) {
; CHECK-NON-MVE-LABEL: fn1:
; CHECK-NON-MVE: @ %bb.0: @ %entry
; CHECK-NON-MVE-NEXT: ldr r1, [r0, #4]
-; CHECK-NON-MVE-NEXT: lsls r2, r1, #8
-; CHECK-NON-MVE-NEXT: movs r3, #3
-; CHECK-NON-MVE-NEXT: str r2, [r0, r3]
-; CHECK-NON-MVE-NEXT: adds r0, r0, #3
-; CHECK-NON-MVE-NEXT: lsrs r1, r1, #24
-; CHECK-NON-MVE-NEXT: strb r1, [r0, #4]
+; CHECK-NON-MVE-NEXT: lsrs r2, r1, #24
+; CHECK-NON-MVE-NEXT: lsls r1, r1, #8
+; CHECK-NON-MVE-NEXT: strb r2, [r0, #7]
+; CHECK-NON-MVE-NEXT: str.w r1, [r0, #3]
; CHECK-NON-MVE-NEXT: bx lr
entry:
%carey = getelementptr inbounds %struct.bar, %struct.bar* %a, i32 0, i32 2
@@ -225,20 +225,12 @@ entry:
%struct.a = type { i96 }
define void @lsll_128bit_shift(%struct.a* nocapture %x) local_unnamed_addr #0 {
-; CHECK-MVE-LABEL: lsll_128bit_shift:
-; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: movs r1, #0
-; CHECK-MVE-NEXT: strd r1, r1, [r0]
-; CHECK-MVE-NEXT: str r1, [r0, #8]
-; CHECK-MVE-NEXT: bx lr
-;
-; CHECK-NON-MVE-LABEL: lsll_128bit_shift:
-; CHECK-NON-MVE: @ %bb.0: @ %entry
-; CHECK-NON-MVE-NEXT: movs r1, #0
-; CHECK-NON-MVE-NEXT: str r1, [r0]
-; CHECK-NON-MVE-NEXT: str r1, [r0, #4]
-; CHECK-NON-MVE-NEXT: str r1, [r0, #8]
-; CHECK-NON-MVE-NEXT: bx lr
+; CHECK-LABEL: lsll_128bit_shift:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: movs r1, #0
+; CHECK-NEXT: strd r1, r1, [r0]
+; CHECK-NEXT: str r1, [r0, #8]
+; CHECK-NEXT: bx lr
entry:
%0 = bitcast %struct.a* %x to i128*
%bf.load = load i128, i128* %0, align 8
@@ -250,29 +242,16 @@ entry:
%struct.b = type { i184 }
define void @lsll_256bit_shift(%struct.b* nocapture %x) local_unnamed_addr #0 {
-; CHECK-MVE-LABEL: lsll_256bit_shift:
-; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: movs r1, #0
-; CHECK-MVE-NEXT: str r1, [r0, #16]
-; CHECK-MVE-NEXT: strd r1, r1, [r0, #8]
-; CHECK-MVE-NEXT: strd r1, r1, [r0]
-; CHECK-MVE-NEXT: ldrb r1, [r0, #23]
-; CHECK-MVE-NEXT: lsls r1, r1, #24
-; CHECK-MVE-NEXT: str r1, [r0, #20]
-; CHECK-MVE-NEXT: bx lr
-;
-; CHECK-NON-MVE-LABEL: lsll_256bit_shift:
-; CHECK-NON-MVE: @ %bb.0: @ %entry
-; CHECK-NON-MVE-NEXT: movs r1, #0
-; CHECK-NON-MVE-NEXT: str r1, [r0, #16]
-; CHECK-NON-MVE-NEXT: str r1, [r0, #8]
-; CHECK-NON-MVE-NEXT: str r1, [r0, #12]
-; CHECK-NON-MVE-NEXT: str r1, [r0]
-; CHECK-NON-MVE-NEXT: str r1, [r0, #4]
-; CHECK-NON-MVE-NEXT: ldrb r1, [r0, #23]
-; CHECK-NON-MVE-NEXT: lsls r1, r1, #24
-; CHECK-NON-MVE-NEXT: str r1, [r0, #20]
-; CHECK-NON-MVE-NEXT: bx lr
+; CHECK-LABEL: lsll_256bit_shift:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: movs r1, #0
+; CHECK-NEXT: str r1, [r0, #16]
+; CHECK-NEXT: strd r1, r1, [r0, #8]
+; CHECK-NEXT: strd r1, r1, [r0]
+; CHECK-NEXT: ldrb r1, [r0, #23]
+; CHECK-NEXT: lsls r1, r1, #24
+; CHECK-NEXT: str r1, [r0, #20]
+; CHECK-NEXT: bx lr
entry:
%0 = bitcast %struct.b* %x to i192*
%bf.load = load i192, i192* %0, align 8
diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-nots.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-nots.mir
index cd60e7be00e0..b3e953964b19 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vpt-nots.mir
+++ b/llvm/test/CodeGen/Thumb2/mve-vpt-nots.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=thumbv8.1-m.main-none-eabi -mattr=+mve -run-pass arm-mve-vpt %s -o - | FileCheck %s
+# RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve -run-pass arm-mve-vpt %s -o - | FileCheck %s
--- |
diff --git a/llvm/test/Transforms/LoopVectorize/ARM/mve-interleaved-cost.ll b/llvm/test/Transforms/LoopVectorize/ARM/mve-interleaved-cost.ll
index 4cd63b422388..1da805f315cc 100644
--- a/llvm/test/Transforms/LoopVectorize/ARM/mve-interleaved-cost.ll
+++ b/llvm/test/Transforms/LoopVectorize/ARM/mve-interleaved-cost.ll
@@ -5,7 +5,7 @@
; REQUIRES: asserts
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
-target triple = "thumbv8.1-m.main-none-eabi"
+target triple = "thumbv8.1m.main-none-eabi"
; Factor 2
diff --git a/llvm/test/Transforms/LoopVectorize/ARM/mve-maskedldst.ll b/llvm/test/Transforms/LoopVectorize/ARM/mve-maskedldst.ll
index 6b036c3b1787..b5d2583cbd5c 100644
--- a/llvm/test/Transforms/LoopVectorize/ARM/mve-maskedldst.ll
+++ b/llvm/test/Transforms/LoopVectorize/ARM/mve-maskedldst.ll
@@ -1,7 +1,7 @@
; RUN: opt -loop-vectorize < %s -S -o - | FileCheck %s
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
-target triple = "thumbv8.1-m.main-none-eabi"
+target triple = "thumbv8.1m.main-none-eabi"
; CHECK-LABEL: test_i32_align4
; CHECK: call void @llvm.masked.store.v4i32.p0v4i32
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