[PATCH] D75601: [AArch64][SVE] Add intrinsics for non-temporal scatters/gathers

Andrzej Warzynski via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Mar 4 03:59:06 PST 2020


andwar created this revision.
andwar added a reviewer: sdesmalen.
Herald added subscribers: llvm-commits, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a reviewer: efriedma.
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andwar marked an inline comment as done.
andwar added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.h:266
   GLDNT1,
+  GLDNT1_INDEX,
   GLDNT1S,
----------------
The new nodes (`GLDNT1_INDEX` and `SSTN1_INDEX`) are only introduced to keep `performGatherLoadCombine` and `performScatterStoreCombine` relatively clean. 

But maybe  I shouldn't introduce them if they're always meant to be replaced with `SPLAT_VECTOR` + `MUL` + `GLDNT1`?


This patch adds the following intrinsics for non-temporal gather loads
and scatter stores:

- aarch64_sve_ldnt1_gather_index
- aarch64_sve_stnt1_scatter_index

These intrinsics implement the "scalar + vector of indices" addressing
mode. As opposed to regular and first-faulting gathers/scatters, there's
no instruction that would take indices and then scale them. Instead, the
indices for non-temporal gathers/scatters are scaled before the
intrinsics are lowered to `ldnt1` instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D75601

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/test/CodeGen/AArch64/sve2-intrinsics-nt-gather-loads-64bit-scaled-offset.ll
  llvm/test/CodeGen/AArch64/sve2-intrinsics-nt-scatter-stores-64bit-scaled-offset.ll

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