[PATCH] D75549: [X86] Match vpmullq latency to uops.info. Correct port usage for 512-bit memory form
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 3 11:17:15 PST 2020
craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel, andreadb.
Herald added subscribers: gbedwell, hiraditya.
Herald added a project: LLVM.
uops.info says these should be 15 cycle instructions. Uops.info also shows the 512-bit form uses port 0 and 5 for both register and memory. We had memory using 0 and 1.
https://reviews.llvm.org/D75549
Files:
llvm/lib/Target/X86/X86SchedSkylakeServer.td
llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512dq.s
llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512dqvl.s
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