[PATCH] D75533: [ARM][LowOverheadLoops] Handle reductions

[Sam Parker via Phabricator via llvm-commits]

samparker created this revision.
samparker added reviewers: SjoerdMeijer, dmgreen.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: LLVM.

While validating live-out values, record instructions that look like a reduction. This will comprise of a vector op (for now only vadd), a vorr (vmov) which store the previous value of vadd and then a vpsel in the exit block which is predicated upon a vctp. This vctp will combine the last two iterations using the vmov and vadd into a vector which can then be consumed by a vaddv.
Once we have determined that it's safe to perform tail-predication, we need to change this sequence of instructions so that the predication doesn't produce incorrect code. This involves changing the register allocation of the vadd so it updates itself and the predication on the final iteration will not update the falsely predicated lanes. This mimics what the vmov, vctp and vpsel do and so we then don't need any of those instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D75533

Files:
  llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
  llvm/lib/CodeGen/ReachingDefAnalysis.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.h
  llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/constant-init-reduction.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/constant-reduction.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/nested-reductions.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions-8-16.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/two-reducing-loops.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll

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