[PATCH] D75522: [compiler-rt][builtins][RISCV] Port __clear_cache to RISC-V Linux

[Luís Marques via Phabricator via llvm-commits]

luismarques created this revision.
luismarques added reviewers: asb, lenary.
Herald added subscribers: llvm-commits, Sanitizers, evandro, sameer.abuasal, s.egerton, Jim, benna, psnobl, PkmX, jfb, rkruppe, rogfer01, shiva0217, kito-cheng, simoncook, krytarowski, dberris.
Herald added projects: Sanitizers, LLVM.

Implements `__clear_cache` for RISC-V Linux.

We can't just use `fence.i` on Linux, because the Linux thread might be scheduled on another hart, and the `fence.i` instruction only flushes the icache of the current hart.

Fixes the failures of the compiler-rt tests `clear_cache_test.c` and `enable_execute_stack_test.c` for RISC-V.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D75522

Files:
  compiler-rt/lib/builtins/clear_cache.c


Index: compiler-rt/lib/builtins/clear_cache.c
===================================================================
--- compiler-rt/lib/builtins/clear_cache.c
+++ compiler-rt/lib/builtins/clear_cache.c
@@ -147,6 +147,16 @@
 
   for (uintptr_t dword = start_dword; dword < end_dword; dword += dword_size)
     __asm__ volatile("flush %0" : : "r"(dword));
+#elif defined(__riscv) && defined(__linux__)
+#define __NR_riscv_flush_icache (244 + 15)
+  register void *start_reg __asm("a0") = start;
+  const register void *end_reg __asm("a1") = end;
+  const register long flags __asm("a2") = 0;
+  const register long syscall_nr __asm("a7") = __NR_riscv_flush_icache;
+  __asm __volatile("ecall"
+                   : "=r"(start_reg)
+                   : "r"(start_reg), "r"(end_reg), "r"(flags), "r"(syscall_nr));
+  assert(start_reg == 0 && "Cache flush syscall failed.");
 #else
 #if __APPLE__
   // On Darwin, sys_icache_invalidate() provides this functionality


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