[PATCH] D75428: [MC][ARM] add implicit immediate form for ldrsbt/ldrht/ldrsht

[Jian Cai via Phabricator via llvm-commits]

jcai19 added a comment.

It seems a multiclass AI3ldrT is used (and only used) to define ldrsbt/ldrht/ldrsht . Maybe we can add one more class in it to handle the implicit immediate? This way we don't need to change ARMAsmParser.cpp. I tried your test cases with a local LLVM patch as below, and seemed it worked,  although I had to remove #-0  from the encoding, e.g. @ CHECK: ldrsht  r5, [r6],               @ encoding: [0xf0,0x50,0x76,0xe0]" instead of "@ CHECK: ldrsht  r5, [r6], #-0           @ encoding: [0xf0,0x50,0x76,0xe0]"

- a/llvm/lib/Target/ARM/ARMInstrInfo.td

+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -2939,6 +2939,16 @@ multiclass AI3ldrT<bits<4> op, string opc> {

    let Inst{11-8} = offset{7-4};
    let Inst{3-0} = offset{3-0};
  }

+  def i0 : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
+                      (ins addr_offset_none:$addr),
+                      IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
+                      "\t$Rt, $addr", "$addr.base = $base_wb", []> {
+    bits<9> offset;
+    let Inst{23} = 0;
+    let Inst{22} = 1;
+    let Inst{11-8} = 0;
+    let Inst{3-0} = 0;
+  }

  def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
                      (ins addr_offset_none:$addr, postidx_reg:$Rm),
                      IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75428/new/

https://reviews.llvm.org/D75428