[PATCH] D75388: Add a pass to identify certain shuffle_vector and transform it into target specific intrinsics.

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Hello. Looks interesting. We ended up doing something similar with lowering of interleaved access groups to VMOVN instructions in MVE. It went straight through ISel though, not needing to go via the InterleavedAccessPass.  I don't immediately see why this case would need to be done differently. It looks like ISel can already generate at least some TBL1 instructions.

Can you add some testcases for this? Both for producing this in the vectorizer/costmodel tests and for the backend codegen of the load+shuffle patterns you expect to see.

Some other initial thoughts:

- Can you run clang-format over the patch. That would lower the amount of noise from the lint bot.
- VF can be calculated from VecTy and Factor.
- Checking the instruction users are a certain kind sounds odd. Can you explain why it's checking that and only generating in those cases?
- I was half expecting BaseT::getInterleavedMemoryOpCost to return something like getMemoryOpCost + getShuffleCost, but it seems to use the cost of inserts + extracts.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D75388/new/

https://reviews.llvm.org/D75388