[llvm] 7d97330 - [AMDGPU] Fix scheduling model for V_MULLIT_F32

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2020-02-28T23:22:58Z
New Revision: 7d973307d5515b44df92f041916a0be25c1faa4b

URL: https://github.com/llvm/llvm-project/commit/7d973307d5515b44df92f041916a0be25c1faa4b
DIFF: https://github.com/llvm/llvm-project/commit/7d973307d5515b44df92f041916a0be25c1faa4b.diff

LOG: [AMDGPU] Fix scheduling model for V_MULLIT_F32

This was incorrectly marked as a half rate 64-bit instruction by D45073.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/VOP3Instructions.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index d3401147d9d5..7478c77f391b 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -396,9 +396,6 @@ def V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_I64_I64_I32>, shl>;
 def V_LSHR_B64 : VOP3Inst <"v_lshr_b64", VOP3_Profile<VOP_I64_I64_I32>, srl>;
 def V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile<VOP_I64_I64_I32>, sra>;
 } // End SubtargetPredicate = isGFX6GFX7
-let SubtargetPredicate = isGFX6GFX7GFX10 in {
-def V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
-} // End SubtargetPredicate = isGFX6GFX7GFX10
 
 let SubtargetPredicate = isGFX8Plus in {
 def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>, lshl_rev>;
@@ -407,6 +404,9 @@ def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>, as
 } // End SubtargetPredicate = isGFX8Plus
 } // End SchedRW = [Write64Bit]
 
+let SubtargetPredicate = isGFX6GFX7GFX10 in {
+def V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
+} // End SubtargetPredicate = isGFX6GFX7GFX10
 
 let SchedRW = [Write32Bit] in {
 let SubtargetPredicate = isGFX8Plus in {