[llvm] e7b9a20 - [Hexagon] Map dcfetch intrinsic to Y2_dcfetchbo, not Y2_dcfetch

[Krzysztof Parzyszek via llvm-commits]

Author: Krzysztof Parzyszek
Date: 2020-02-28T14:19:20-06:00
New Revision: e7b9a20584a51c6ed76ca4873ce501bd422d0a75

URL: https://github.com/llvm/llvm-project/commit/e7b9a20584a51c6ed76ca4873ce501bd422d0a75
DIFF: https://github.com/llvm/llvm-project/commit/e7b9a20584a51c6ed76ca4873ce501bd422d0a75.diff

LOG: [Hexagon] Map dcfetch intrinsic to Y2_dcfetchbo, not Y2_dcfetch

Added: 
    llvm/test/CodeGen/Hexagon/isel-dcfetch-intrin-map.ll

Modified: 
    llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td
    llvm/lib/Target/Hexagon/HexagonIntrinsics.td

Removed: 
    


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diff  --git a/llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td b/llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td
index d8d55b70f7e0..e9e009624ff8 100644
--- a/llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td
+++ b/llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td
@@ -1657,8 +1657,6 @@ def: Pat<(int_hexagon_S2_interleave DoubleRegs:$src1),
          (S2_interleave DoubleRegs:$src1)>, Requires<[HasV5]>;
 def: Pat<(int_hexagon_S2_deinterleave DoubleRegs:$src1),
          (S2_deinterleave DoubleRegs:$src1)>, Requires<[HasV5]>;
-def: Pat<(int_hexagon_Y2_dcfetch IntRegs:$src1),
-         (Y2_dcfetch IntRegs:$src1)>, Requires<[HasV5]>;
 def: Pat<(int_hexagon_Y2_dczeroa IntRegs:$src1),
          (Y2_dczeroa IntRegs:$src1)>, Requires<[HasV5]>;
 def: Pat<(int_hexagon_Y2_dccleana IntRegs:$src1),

diff  --git a/llvm/lib/Target/Hexagon/HexagonIntrinsics.td b/llvm/lib/Target/Hexagon/HexagonIntrinsics.td
index 4f0e7e8ed2cc..df6b63c19fa6 100644
--- a/llvm/lib/Target/Hexagon/HexagonIntrinsics.td
+++ b/llvm/lib/Target/Hexagon/HexagonIntrinsics.td
@@ -236,6 +236,8 @@ def: T_R_pat<Y2_dczeroa,     int_hexagon_Y2_dczeroa>;
 def: T_RR_pat<Y4_l2fetch,    int_hexagon_Y4_l2fetch>;
 def: T_RP_pat<Y5_l2fetch,    int_hexagon_Y5_l2fetch>;
 
+def: Pat<(int_hexagon_Y2_dcfetch I32:$Rt), (Y2_dcfetchbo I32:$Rt, 0)>;
+
 //
 // Patterns for optimizing code generations for HVX.
 

diff  --git a/llvm/test/CodeGen/Hexagon/isel-dcfetch-intrin-map.ll b/llvm/test/CodeGen/Hexagon/isel-dcfetch-intrin-map.ll
new file mode 100644
index 000000000000..6e9f1af74bd3
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/isel-dcfetch-intrin-map.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; Check that intrinsic int_hexagon_Y2_dcfetch is mapped to Y2_dcfetchbo
+; (not Y2_dcfetch).
+
+; CHECK: dcfetch(r0+#0)
+
+target triple = "hexagon"
+
+define void @fred(i8* %a0) #0 {
+  call void @llvm.hexagon.Y2.dcfetch(i8* %a0)
+  ret void
+}
+
+declare void @llvm.hexagon.Y2.dcfetch(i8*) #0
+
+attributes #0 = { nounwind }
+