[PATCH] D75371: [ARM] Optimise ASRL/LSRL to smaller shifts using demand bits.

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: simon_tatham, samparker, SjoerdMeijer, ostannard.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: LLVM.

The ASRL/LSRL long shifts are generated from 64bit shifts. Once we have them, it might turn out that enough of the 64bit result was not required that we can use a smaller shift to perform the same result. As the smaller shift can in general be folded in more way, such as into add instructions in one of the test cases here, we can use the demand bit analysis to prefer the smaller shifts where we can.


https://reviews.llvm.org/D75371

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/test/CodeGen/ARM/shift_parts.ll
  llvm/test/CodeGen/Thumb2/fir.ll

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