[PATCH] D57059: [SLP] Initial support for the vectorization of the non-power-of-2 vectors.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/test/Transforms/SLPVectorizer/X86/zext.ll:263
+; SLM-NEXT:    [[TMP20:%.*]] = extractelement <2 x i16> [[TMP12]], i32 1
+; SLM-NEXT:    [[V7:%.*]] = insertelement <8 x i16> [[V6]], i16 [[TMP20]], i32 7
 ; SLM-NEXT:    ret <8 x i16> [[V7]]
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Its really odd that SLM fails to use zext <8 x i8> to <8 x i16> like SSE2, I think the custom SLM extract/insert costs are affecting something unexpected?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57059/new/

https://reviews.llvm.org/D57059