[llvm] b4207e7 - [ARM][Thumb2] Support .w assembler qualifier for pld/pldw/pli
Oliver Stannard via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 28 03:08:40 PST 2020
Author: Stefan Agner
Date: 2020-02-28T11:08:24Z
New Revision: b4207e705b2b037d75876f10d12b730685020d94
URL: https://github.com/llvm/llvm-project/commit/b4207e705b2b037d75876f10d12b730685020d94
DIFF: https://github.com/llvm/llvm-project/commit/b4207e705b2b037d75876f10d12b730685020d94.diff
LOG: [ARM][Thumb2] Support .w assembler qualifier for pld/pldw/pli
Accept explicit wide assembler qualifier for the pld/pldw/pli.
Differential revision: https://reviews.llvm.org/D75144
Added:
Modified:
llvm/lib/Target/ARM/ARMInstrThumb2.td
llvm/test/MC/ARM/basic-thumb2-instructions.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td
index 1a9237b5afcf..270e9bca7735 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -1871,6 +1871,34 @@ defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
+// PLD/PLDW/PLI aliases w/ the optional .w suffix
+def : t2InstAlias<"pld${p}.w\t$addr",
+ (t2PLDi12 t2addrmode_imm12:$addr, pred:$p)>;
+def : t2InstAlias<"pld${p}.w\t$addr",
+ (t2PLDi8 t2addrmode_negimm8:$addr, pred:$p)>;
+def : t2InstAlias<"pld${p}.w\t$addr",
+ (t2PLDs t2addrmode_so_reg:$addr, pred:$p)>;
+
+def : InstAlias<"pldw${p}.w\t$addr",
+ (t2PLDWi12 t2addrmode_imm12:$addr, pred:$p), 0>,
+ Requires<[IsThumb2,HasV7,HasMP]>;
+def : InstAlias<"pldw${p}.w\t$addr",
+ (t2PLDWi8 t2addrmode_negimm8:$addr, pred:$p), 0>,
+ Requires<[IsThumb2,HasV7,HasMP]>;
+def : InstAlias<"pldw${p}.w\t$addr",
+ (t2PLDWs t2addrmode_so_reg:$addr, pred:$p), 0>,
+ Requires<[IsThumb2,HasV7,HasMP]>;
+
+def : InstAlias<"pli${p}.w\t$addr",
+ (t2PLIi12 t2addrmode_imm12:$addr, pred:$p), 0>,
+ Requires<[IsThumb2,HasV7]>;
+def : InstAlias<"pli${p}.w\t$addr",
+ (t2PLIi8 t2addrmode_negimm8:$addr, pred:$p), 0>,
+ Requires<[IsThumb2,HasV7]>;
+def : InstAlias<"pli${p}.w\t$addr",
+ (t2PLIs t2addrmode_so_reg:$addr, pred:$p), 0>,
+ Requires<[IsThumb2,HasV7]>;
+
// pci variant is very similar to i12, but supports negative offsets
// from the PC. Only PLD and PLI have pci variants (not PLDW)
class T2Iplpci<bits<1> inst, string opc> : T2Iso<(outs), (ins t2ldrlabel:$addr),
@@ -1893,6 +1921,24 @@ class T2Iplpci<bits<1> inst, string opc> : T2Iso<(outs), (ins t2ldrlabel:$addr),
def t2PLDpci : T2Iplpci<0, "pld">, Requires<[IsThumb2]>;
def t2PLIpci : T2Iplpci<1, "pli">, Requires<[IsThumb2,HasV7]>;
+def : t2InstAlias<"pld${p}.w $addr",
+ (t2PLDpci t2ldrlabel:$addr, pred:$p)>;
+def : InstAlias<"pli${p}.w $addr",
+ (t2PLIpci t2ldrlabel:$addr, pred:$p), 0>,
+ Requires<[IsThumb2,HasV7]>;
+
+// PLD/PLI with alternate literal form.
+def : t2InstAlias<"pld${p} $addr",
+ (t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>;
+def : InstAlias<"pli${p} $addr",
+ (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p), 0>,
+ Requires<[IsThumb2,HasV7]>;
+def : t2InstAlias<"pld${p}.w $addr",
+ (t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>;
+def : InstAlias<"pli${p}.w $addr",
+ (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p), 0>,
+ Requires<[IsThumb2,HasV7]>;
+
//===----------------------------------------------------------------------===//
// Load / store multiple Instructions.
//
@@ -5184,14 +5230,6 @@ def : t2InstAlias<"ldr${p}.w $Rt, $immediate",
(t2LDRConstPool GPRnopc:$Rt,
const_pool_asm_imm:$immediate, pred:$p)>;
-// PLD/PLDW/PLI with alternate literal form.
-def : t2InstAlias<"pld${p} $addr",
- (t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>;
-def : InstAlias<"pli${p} $addr",
- (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p), 0>,
- Requires<[IsThumb2,HasV7]>;
-
-
//===----------------------------------------------------------------------===//
// ARMv8.1m instructions
//
diff --git a/llvm/test/MC/ARM/basic-thumb2-instructions.s b/llvm/test/MC/ARM/basic-thumb2-instructions.s
index f490538011af..d344b6601964 100644
--- a/llvm/test/MC/ARM/basic-thumb2-instructions.s
+++ b/llvm/test/MC/ARM/basic-thumb2-instructions.s
@@ -1929,6 +1929,7 @@ adds sp, #-4096
pld [r7, #257]
pld [r1, #0]
pld [r1, #-0]
+ pld.w [r1, #-0]
@ CHECK: pld [r5, #-4] @ encoding: [0x15,0xf8,0x04,0xfc]
@ CHECK: pld [r6, #32] @ encoding: [0x96,0xf8,0x20,0xf0]
@@ -1937,6 +1938,7 @@ adds sp, #-4096
@ CHECK: pld [r7, #257] @ encoding: [0x97,0xf8,0x01,0xf1]
@ CHECK: pld [r1] @ encoding: [0x91,0xf8,0x00,0xf0]
@ CHECK: pld [r1, #-0] @ encoding: [0x11,0xf8,0x00,0xfc]
+@ CHECK: pld [r1, #-0] @ encoding: [0x11,0xf8,0x00,0xfc]
@------------------------------------------------------------------------------
@@ -1948,6 +1950,8 @@ adds sp, #-4096
@ fixup A - offset: 0, value: _foo, kind: fixup_t2_ldst_pcrel_12
pld [pc,#-4095]
+ pld.w [pc,#-4095]
+@ CHECK: pld [pc, #-4095] @ encoding: [0x1f,0xf8,0xff,0xff]
@ CHECK: pld [pc, #-4095] @ encoding: [0x1f,0xf8,0xff,0xff]
@@ -1956,17 +1960,21 @@ adds sp, #-4096
@------------------------------------------------------------------------------
pld [r8, r1]
pld [r5, r2]
+ pld.w [r5, r2]
pld [r0, r2, lsl #3]
pld [r8, r2, lsl #2]
pld [sp, r2, lsl #1]
pld [sp, r2, lsl #0]
+ pld.w [sp, r2, lsl #1]
@ CHECK: pld [r8, r1] @ encoding: [0x18,0xf8,0x01,0xf0]
@ CHECK: pld [r5, r2] @ encoding: [0x15,0xf8,0x02,0xf0]
+@ CHECK: pld [r5, r2] @ encoding: [0x15,0xf8,0x02,0xf0]
@ CHECK: pld [r0, r2, lsl #3] @ encoding: [0x10,0xf8,0x32,0xf0]
@ CHECK: pld [r8, r2, lsl #2] @ encoding: [0x18,0xf8,0x22,0xf0]
@ CHECK: pld [sp, r2, lsl #1] @ encoding: [0x1d,0xf8,0x12,0xf0]
@ CHECK: pld [sp, r2] @ encoding: [0x1d,0xf8,0x02,0xf0]
+@ CHECK: pld [sp, r2, lsl #1] @ encoding: [0x1d,0xf8,0x12,0xf0]
@------------------------------------------------------------------------------
@ PLI(immediate)
@@ -1978,6 +1986,7 @@ adds sp, #-4096
pli [r7, #257]
pli [pc, #+4095]
pli [pc, #-4095]
+ pli.w [pc, #-4095]
@ CHECK: pli [r5, #-4] @ encoding: [0x15,0xf9,0x04,0xfc]
@ CHECK: pli [r6, #32] @ encoding: [0x96,0xf9,0x20,0xf0]
@@ -1986,6 +1995,7 @@ adds sp, #-4096
@ CHECK: pli [r7, #257] @ encoding: [0x97,0xf9,0x01,0xf1]
@ CHECK: pli [pc, #4095] @ encoding: [0x9f,0xf9,0xff,0xff]
@ CHECK: pli [pc, #-4095] @ encoding: [0x1f,0xf9,0xff,0xff]
+@ CHECK: pli [pc, #-4095] @ encoding: [0x1f,0xf9,0xff,0xff]
@------------------------------------------------------------------------------
@@ -2003,17 +2013,21 @@ adds sp, #-4096
@------------------------------------------------------------------------------
pli [r8, r1]
pli [r5, r2]
+ pli.w [r5, r2]
pli [r0, r2, lsl #3]
pli [r8, r2, lsl #2]
pli [sp, r2, lsl #1]
pli [sp, r2, lsl #0]
+ pli.w [sp, r2, lsl #1]
@ CHECK: pli [r8, r1] @ encoding: [0x18,0xf9,0x01,0xf0]
@ CHECK: pli [r5, r2] @ encoding: [0x15,0xf9,0x02,0xf0]
+@ CHECK: pli [r5, r2] @ encoding: [0x15,0xf9,0x02,0xf0]
@ CHECK: pli [r0, r2, lsl #3] @ encoding: [0x10,0xf9,0x32,0xf0]
@ CHECK: pli [r8, r2, lsl #2] @ encoding: [0x18,0xf9,0x22,0xf0]
@ CHECK: pli [sp, r2, lsl #1] @ encoding: [0x1d,0xf9,0x12,0xf0]
@ CHECK: pli [sp, r2] @ encoding: [0x1d,0xf9,0x02,0xf0]
+@ CHECK: pli [sp, r2, lsl #1] @ encoding: [0x1d,0xf9,0x12,0xf0]
@------------------------------------------------------------------------------
@ POP (alias)
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