[PATCH] D75326: [entry values] X86: Describe effects of MOV{8,16}ri (PR45053)
Djordje Todorovic via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 28 02:37:41 PST 2020
djtodoro added inline comments.
================
Comment at: llvm/lib/Target/X86/X86InstrInfo.cpp:7795
// 64-bit parameters, so we need to consider super-registers.
if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
return None;
----------------
dstenb wrote:
> At least when I tried this out on a 8th generation i7, it seems that MOV8ri and MOV16ri do not modify the upper bits in super-registers.
>
> ```
> movl $287454020, %edi # imm = 0x11223344
> mov $21862, %di # imm = 0x5566
> movb $119, %dil # imm = 0x77
> callq call
> ```
>
> That produces the value 0x11225577.
>
> In this test case we try to describe:
>
> ```
> renamable $rsi = LEA64r $rip, 1, $noreg, @.str, $noreg, debug-location !51
> renamable $si = MOV16ri 2112
> ```
>
> As `Reg` is a 32-bit register, I think we want to return something like this for the MOV16ri instruction:
>
> ```
> ParamLoadedValue(Reg, (DW_OP_constu, 0xFFFF0000, DW_OP_and, DW_OP_constu, MI.getOperand(1).getImm(), DW_OP_or))
> ```
>
>
>At least when I tried this out on a 8th generation i7, it seems that MOV8ri and MOV16ri do not modify the upper bits in super-registers.
I have not tried debugging it, but I guess this would result a wrong value printed within debugger, and we need this:
>As Reg is a 32-bit register, I think we want to return something like this for the MOV16ri instruction:
>ParamLoadedValue(Reg, (DW_OP_constu, 0xFFFF0000, DW_OP_and, DW_OP_constu, MI.getOperand(1).getImm(), DW_OP_or))
If that is the case, I agree with that. So the `X86::MOV8ri` and `X86::MOV16ri`should be handled as a special case here.
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https://reviews.llvm.org/D75326/new/
https://reviews.llvm.org/D75326
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