[llvm] 6afc3de - [AVR] Fix private label prefix
Ayke van Laethem via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 26 11:32:38 PST 2020
Author: Ayke van Laethem
Date: 2020-02-26T20:32:25+01:00
New Revision: 6afc3de42f8f65dfa2e51b0e81e95ef6427be9ac
URL: https://github.com/llvm/llvm-project/commit/6afc3de42f8f65dfa2e51b0e81e95ef6427be9ac
DIFF: https://github.com/llvm/llvm-project/commit/6afc3de42f8f65dfa2e51b0e81e95ef6427be9ac.diff
LOG: [AVR] Fix private label prefix
This is a small pet peeve from me. This change makes sure the AVR backend uses
the correct private label prefix (.L) so that private labels are hidden in
avr-objdump.
Example code:
define i8 @foo(i1 %cond) {
br i1 %cond, label %then, label %else
then:
ret i8 3
else:
ret i8 5
}
When compiling this:
llc -march=avr -filetype=obj -o test.o test.ll
and then dumping it:
avr-objdump -d test.o
You would previously get an ugly temporary label:
00000000 <foo>:
0: 81 70 andi r24, 0x01 ; 1
2: 80 30 cpi r24, 0x00 ; 0
4: f9 f3 breq .-2 ; 0x4 <foo+0x4>
6: 83 e0 ldi r24, 0x03 ; 3
8: 08 95 ret
0000000a <LBB0_2>:
a: 85 e0 ldi r24, 0x05 ; 5
c: 08 95 ret
This patch fixes that, the output is now:
00000000 <foo>:
0: 81 70 andi r24, 0x01 ; 1
2: 80 30 cpi r24, 0x00 ; 0
4: 01 f0 breq .+0 ; 0x6 <foo+0x6>
6: 83 e0 ldi r24, 0x03 ; 3
8: 08 95 ret
a: 85 e0 ldi r24, 0x05 ; 5
c: 08 95 ret
Note that as you can see the breq operand is different. However it is
still the same after linking:
4: 11 f0 breq .+4
Differential Revision: https://reviews.llvm.org/D75124
Added:
Modified:
llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp
llvm/test/CodeGen/AVR/branch-relaxation-long.ll
llvm/test/CodeGen/AVR/branch-relaxation.ll
llvm/test/CodeGen/AVR/ctlz.ll
llvm/test/CodeGen/AVR/cttz.ll
llvm/test/CodeGen/AVR/integration/blink.ll
llvm/test/CodeGen/AVR/rot.ll
llvm/test/CodeGen/AVR/smul-with-overflow.ll
llvm/test/CodeGen/AVR/umul-with-overflow.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp
index c25a2b232013..4fb6d3054464 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp
@@ -21,6 +21,7 @@ AVRMCAsmInfo::AVRMCAsmInfo(const Triple &TT, const MCTargetOptions &Options) {
CalleeSaveStackSlotSize = 2;
CommentString = ";";
PrivateGlobalPrefix = ".L";
+ PrivateLabelPrefix = ".L";
UsesELFSectionDirectiveForBSS = true;
UseIntegratedAssembler = true;
SupportsDebugInformation = true;
diff --git a/llvm/test/CodeGen/AVR/branch-relaxation-long.ll b/llvm/test/CodeGen/AVR/branch-relaxation-long.ll
index 2cfc7e812ebc..e3e9a6f1d02e 100644
--- a/llvm/test/CodeGen/AVR/branch-relaxation-long.ll
+++ b/llvm/test/CodeGen/AVR/branch-relaxation-long.ll
@@ -2,8 +2,8 @@
; CHECK-LABEL: relax_to_jmp:
; CHECK: cpi r{{[0-9]+}}, 0
-; CHECK: brne [[BB1:LBB[0-9]+_[0-9]+]]
-; CHECK: jmp [[BB2:LBB[0-9]+_[0-9]+]]
+; CHECK: brne [[BB1:.LBB[0-9]+_[0-9]+]]
+; CHECK: jmp [[BB2:.LBB[0-9]+_[0-9]+]]
; CHECK: [[BB1]]:
; CHECK: nop
; CHECK: [[BB2]]:
@@ -2069,10 +2069,10 @@ finished:
}
; CHECK-LABEL: relax_to_jmp_backwards:
-; CHECK: [[BB1:LBB[0-9]+_[0-9]+]]
+; CHECK: [[BB1:.LBB[0-9]+_[0-9]+]]
; CHECK: nop
; CHECK: cpi r{{[0-9]+}}, 0
-; CHECK: breq [[BB2:LBB[0-9]+_[0-9]+]]
+; CHECK: breq [[BB2:.LBB[0-9]+_[0-9]+]]
; CHECK: jmp [[BB1]]
; CHECK: [[BB2]]:
define i8 @relax_to_jmp_backwards(i1 %a) {
diff --git a/llvm/test/CodeGen/AVR/branch-relaxation.ll b/llvm/test/CodeGen/AVR/branch-relaxation.ll
index e415b059692e..cee3963c1ee3 100644
--- a/llvm/test/CodeGen/AVR/branch-relaxation.ll
+++ b/llvm/test/CodeGen/AVR/branch-relaxation.ll
@@ -2,9 +2,9 @@
; CHECK-LABEL: relax_breq
; CHECK: cpi r{{[0-9]+}}, 0
-; CHECK: brne LBB0_1
-; CHECK: rjmp LBB0_2
-; LBB0_1:
+; CHECK: brne .LBB0_1
+; CHECK: rjmp .LBB0_2
+; .LBB0_1:
define i8 @relax_breq(i1 %a) {
entry-block:
@@ -68,10 +68,10 @@ finished:
; CHECK-LABEL: no_relax_breq
; CHECK: cpi r{{[0-9]+}}, 0
-; CHECK: breq [[END_BB:LBB[0-9]+_[0-9]+]]
+; CHECK: breq [[END_BB:.LBB[0-9]+_[0-9]+]]
; CHECK: nop
; ...
-; LBB0_1:
+; .LBB0_1:
define i8 @no_relax_breq(i1 %a) {
entry-block:
br i1 %a, label %hello, label %finished
diff --git a/llvm/test/CodeGen/AVR/ctlz.ll b/llvm/test/CodeGen/AVR/ctlz.ll
index 8659550baf90..8681b8a3f1f5 100644
--- a/llvm/test/CodeGen/AVR/ctlz.ll
+++ b/llvm/test/CodeGen/AVR/ctlz.ll
@@ -10,8 +10,8 @@ declare i8 @llvm.ctlz.i8(i8)
; CHECK-LABEL: count_leading_zeros:
; CHECK: cpi [[RESULT:r[0-9]+]], 0
-; CHECK: brne LBB0_1
-; CHECK: rjmp LBB0_2
+; CHECK: brne .LBB0_1
+; CHECK: rjmp .LBB0_2
; CHECK: mov [[SCRATCH:r[0-9]+]], {{.*}}[[RESULT]]
; CHECK: lsr {{.*}}[[SCRATCH]]
; CHECK: or {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
diff --git a/llvm/test/CodeGen/AVR/cttz.ll b/llvm/test/CodeGen/AVR/cttz.ll
index 02d36954f526..60ba57edcab7 100644
--- a/llvm/test/CodeGen/AVR/cttz.ll
+++ b/llvm/test/CodeGen/AVR/cttz.ll
@@ -10,7 +10,7 @@ declare i8 @llvm.cttz.i8(i8)
; CHECK-LABEL: count_trailing_zeros:
; CHECK: cpi [[RESULT:r[0-9]+]], 0
-; CHECK: breq [[END_BB:LBB[0-9]+_[0-9]+]]
+; CHECK: breq [[END_BB:.LBB[0-9]+_[0-9]+]]
; CHECK: mov [[SCRATCH:r[0-9]+]], {{.*}}[[RESULT]]
; CHECK: dec {{.*}}[[SCRATCH]]
; CHECK: com {{.*}}[[RESULT]]
diff --git a/llvm/test/CodeGen/AVR/integration/blink.ll b/llvm/test/CodeGen/AVR/integration/blink.ll
index 29c3b7f48ff1..76d3d9ff75b9 100644
--- a/llvm/test/CodeGen/AVR/integration/blink.ll
+++ b/llvm/test/CodeGen/AVR/integration/blink.ll
@@ -89,7 +89,7 @@ entry:
br label %while.body
-; CHECK-LABEL: LBB3_1
+; CHECK-LABEL: .LBB3_1
while.body:
; CHECK: call turn_on
@@ -98,6 +98,6 @@ while.body:
; CHECK-NEXT: call turn_off
call void @turn_off()
- ; CHECK-NEXT: rjmp LBB3_1
+ ; CHECK-NEXT: rjmp .LBB3_1
br label %while.body
}
diff --git a/llvm/test/CodeGen/AVR/rot.ll b/llvm/test/CodeGen/AVR/rot.ll
index 49981aabe7c3..315423429954 100644
--- a/llvm/test/CodeGen/AVR/rot.ll
+++ b/llvm/test/CodeGen/AVR/rot.ll
@@ -7,15 +7,15 @@ define i8 @rol8(i8 %val, i8 %amt) {
; CHECK: andi r22, 7
; CHECK-NEXT: cpi r22, 0
- ; CHECK-NEXT: breq LBB0_2
+ ; CHECK-NEXT: breq .LBB0_2
-; CHECK-NEXT: LBB0_1:
+; CHECK-NEXT: .LBB0_1:
; CHECK-NEXT: lsl r24
; CHECK-NEXT: adc r24, r1
; CHECK-NEXT: subi r22, 1
- ; CHECK-NEXT: brne LBB0_1
+ ; CHECK-NEXT: brne .LBB0_1
-; CHECK-NEXT:LBB0_2:
+; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: ret
%mod = urem i8 %amt, 8
@@ -34,17 +34,17 @@ define i8 @ror8(i8 %val, i8 %amt) {
; CHECK: andi r22, 7
; CHECK-NEXT: cpi r22, 0
- ; CHECK-NEXT: breq LBB1_2
+ ; CHECK-NEXT: breq .LBB1_2
-; CHECK-NEXT: LBB1_1:
+; CHECK-NEXT: .LBB1_1:
; CHECK-NEXT: lsr r24
; CHECK-NEXT: ldi r0, 0
; CHECK-NEXT: ror r0
; CHECK-NEXT: or r24, r0
; CHECK-NEXT: subi r22, 1
- ; CHECK-NEXT: brne LBB1_1
+ ; CHECK-NEXT: brne .LBB1_1
-; CHECK-NEXT:LBB1_2:
+; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: ret
%mod = urem i8 %amt, 8
diff --git a/llvm/test/CodeGen/AVR/smul-with-overflow.ll b/llvm/test/CodeGen/AVR/smul-with-overflow.ll
index 9eb2c7411dee..4004f1bddbdc 100644
--- a/llvm/test/CodeGen/AVR/smul-with-overflow.ll
+++ b/llvm/test/CodeGen/AVR/smul-with-overflow.ll
@@ -22,7 +22,7 @@ entry-block:
; CHECK: asr {{.*}}[[LOW]]
; CHECK: ldi [[RET:r[0-9]+]], 1
; CHECK: cp {{.*}}[[HIGH]], {{.*}}[[LOW]]
-; CHECK: brne [[LABEL:LBB[_0-9]+]]
+; CHECK: brne [[LABEL:.LBB[_0-9]+]]
; CHECK: ldi {{.*}}[[RET]], 0
; CHECK: {{.*}}[[LABEL]]
; CHECK: ret
diff --git a/llvm/test/CodeGen/AVR/umul-with-overflow.ll b/llvm/test/CodeGen/AVR/umul-with-overflow.ll
index c6457552dea8..c3c4a30f87cc 100644
--- a/llvm/test/CodeGen/AVR/umul-with-overflow.ll
+++ b/llvm/test/CodeGen/AVR/umul-with-overflow.ll
@@ -13,7 +13,7 @@ entry-block:
; CHECK: mov [[HIGH:r[0-9]+]], r1
; CHECK: ldi [[RET:r[0-9]+]], 1
; CHECK: cpi {{.*}}[[HIGH]], 0
-; CHECK: brne [[LABEL:LBB[_0-9]+]]
+; CHECK: brne [[LABEL:.LBB[_0-9]+]]
; CHECK: ldi {{.*}}[[RET]], 0
; CHECK: {{.*}}[[LABEL]]
; CHECK: ret
More information about the llvm-commits
mailing list