[PATCH] D75157: [DAGCombine] Perform the fold of A - (-B) -> A + B only when it is cheaper

[qshanz via Phabricator via llvm-commits]

steven.zhang created this revision.
steven.zhang added reviewers: rampitec, RKSimon, craig.topper, spatel, dmgreen, arsenm, jsji, PowerPC.
Herald added subscribers: llvm-commits, kerbowa, hiraditya, nhaehnle, wdng, jvesely, nemanjai.
Herald added a project: LLVM.

We have the rule to fold A + B -> A - (-B) only when it is cheaper.

  // fold (fadd A, (fneg B)) -> (fsub A, B)
  if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
      TLI.getNegatibleCost(N1, DAG, LegalOperations, ForCodeSize) ==
          TargetLowering::NegatibleCost::Cheaper)
    return DAG.getNode(
        ISD::FSUB, DL, VT, N0,
        TLI.getNegatedExpression(N1, DAG, LegalOperations, ForCodeSize), Flags);

But for the reverse folding, it is done as long as it is not expensive, which including that it is neutral. This patch fix this transformation that didn't have any gain.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D75157

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AMDGPU/fma-combine.ll
  llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
  llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll
  llvm/test/CodeGen/AMDGPU/fsub.f16.ll
  llvm/test/CodeGen/AMDGPU/reduction.ll
  llvm/test/CodeGen/AMDGPU/v_mac.ll
  llvm/test/CodeGen/PowerPC/qpx-recipest.ll
  llvm/test/CodeGen/X86/dag-fmf-cse.ll
  llvm/test/CodeGen/X86/fma_patterns.ll
  llvm/test/CodeGen/X86/fma_patterns_wide.ll
  llvm/test/CodeGen/X86/fp-fold.ll
  llvm/test/CodeGen/X86/fp_constant_op.ll
  llvm/test/CodeGen/X86/limited-prec.ll
  llvm/test/CodeGen/X86/load-scalar-as-vector.ll
  llvm/test/CodeGen/X86/negative-sin.ll
  llvm/test/CodeGen/X86/pr44749.ll
  llvm/test/CodeGen/X86/vec_ss_load_fold.ll

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