[PATCH] D75138: [WIP][AMDGPU] Eliminate the ScratchWaveOffset register from the calling convention

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

I assume this is missing a lot of test updates?



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Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:602-603
+
+    // Save and restore SRSRC bits [48:63]. We only want to update the base
+    // address in bits [0:47].
+    BuildMI(MBB, I, DL, TII->get(AMDGPU::S_AND_B32), SavedWord)
----------------
Do we actually need these bits? I'm fairly confident these are always 0 in the HSA resource descriptor (or at least are a known constant we can just reproduce later)


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Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:606
+        .addReg(ScratchRsrcSub1)
+        .addImm(0xffff << 0x10);
+
----------------
I think just 0xffff0000 would be clearer here


================
Comment at: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h:340
+  // function, this is 0.
   unsigned FrameOffsetReg = AMDGPU::FP_REG;
 
----------------
These should be switched to Register at some point


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Comment at: llvm/test/CodeGen/AMDGPU/cc-update-scavenge-fail.ll:5
+
+; XFAIL: *
+
----------------
I would move this to the first line, and check the error message to make sure it fails for the right reason


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D75138/new/

https://reviews.llvm.org/D75138