[PATCH] D75114: [DAG] MatchRotate - Add funnel shift by immediate support

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


================
Comment at: llvm/test/CodeGen/X86/avg.ll:2708-2736
+; AVX512F-NEXT:    movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; AVX512F-NEXT:    addq $-1, %r8
+; AVX512F-NEXT:    movq %r8, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; AVX512F-NEXT:    movl $0, %eax
+; AVX512F-NEXT:    adcq $-1, %rax
+; AVX512F-NEXT:    movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; AVX512F-NEXT:    addq $-1, %rdi
----------------
All this doesn't look like an improvement,
but i suspect this is an unrelated codegen issue
that is only being exposed by the change.


================
Comment at: llvm/test/CodeGen/X86/bitreverse.ll:1114
+; X64-NEXT:    shrdq $48, %rdx, %rcx
+; X64-NEXT:    movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; X64-NEXT:    movq %rcx, 56(%rax)
----------------
Technically this implies more registers are being used here,
not sure what that says about the actual asm change.


================
Comment at: llvm/test/CodeGen/X86/known-bits.ll:123
 ; X64-NEXT:    addq %rdi, %rsi
-; X64-NEXT:    adcl $0, %edx
+; X64-NEXT:    adcq $0, %rdx
 ; X64-NEXT:    shldq $54, %rsi, %rdx
----------------
Demandedbits failure? (no longer narrowed into 32-bit)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75114/new/

https://reviews.llvm.org/D75114