[PATCH] D74338: [RFC][TableGen] Support combining AssemblerPredicates with ORs

[Simon Cook via Phabricator via llvm-commits]

simoncook updated this revision to Diff 246174.
simoncook retitled this revision from "[RFC][TableGen/RISCV] Support combining AssemblerPredicates with ORs" to "[RFC][TableGen] Support combining AssemblerPredicates with ORs".
simoncook edited the summary of this revision.
simoncook set the repository for this revision to rG LLVM Github Monorepo.
simoncook added a comment.
Herald added subscribers: kerbowa, jfb, atanasyan, fedor.sergeev, aheejin, jgravelle-google, sbc100, jvesely, sdardis, dylanmckay, jyknight, dschuff, arsenm.

Following feedback from @nhaehnle (http://lists.llvm.org/pipermail/llvm-dev/2020-February/139186.html) I have re-designed this to look more TableGen like (i.e. using DAGs instead of strings to describe the predicate).  I have declared two operators `any_of` and `all_of` which I think read better than `and` and `or` in these cases when just looking at the target files.

- I have removed the RISC-V bitmanip changes I want to support (I'll rebase D65649 <https://reviews.llvm.org/D65649> on this to remove the circular dependency).
- Added tests for existing functionality and new or functionality.
- Changes to all backends are mechanical, no functional changes are intended, everything still passes with `ninja check-llvm` on my side.

I may need to improve some of the emitters I've touched, in particular RISCVCompressInstEmitter, but I think this is sufficient to carry on discussing the method of my proposed change.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74338/new/

https://reviews.llvm.org/D74338

Files:
  llvm/include/llvm/MC/MCInstPrinter.h
  llvm/include/llvm/Target/Target.td
  llvm/lib/MC/MCInstPrinter.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AArch64SystemOperands.td
  llvm/lib/Target/AMDGPU/AMDGPU.td
  llvm/lib/Target/AMDGPU/SIInstrInfo.td
  llvm/lib/Target/ARM/ARMPredicates.td
  llvm/lib/Target/AVR/AVRInstrInfo.td
  llvm/lib/Target/Hexagon/Hexagon.td
  llvm/lib/Target/Hexagon/HexagonDepArch.td
  llvm/lib/Target/Mips/Mips.td
  llvm/lib/Target/Mips/MipsDSPInstrFormats.td
  llvm/lib/Target/Mips/MipsInstrFPU.td
  llvm/lib/Target/Mips/MipsInstrInfo.td
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/Sparc/SparcInstrInfo.td
  llvm/lib/Target/SystemZ/SystemZFeatures.td
  llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/test/TableGen/AsmPredicateCombining.td
  llvm/test/TableGen/AsmPredicateCombiningRISCV.td
  llvm/test/TableGen/AsmPredicateCondsEmission.td
  llvm/utils/TableGen/AsmWriterEmitter.cpp
  llvm/utils/TableGen/FixedLenDecoderEmitter.cpp
  llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
  llvm/utils/TableGen/SubtargetFeatureInfo.cpp

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