[PATCH] D74049: [AVR] Implement disassembly support for I/O instructions

[Dylan McKay via Phabricator via llvm-commits]

dylanmckay requested changes to this revision.
dylanmckay added inline comments.
This revision now requires changes to proceed.


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Comment at: llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp:116
+  Inst.addOperand(MCOperand::createImm(addr));
+  if (DecodeGPR8RegisterClass(Inst, reg, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+  return MCDisassembler::Success;
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Place the early return on a new line for visibility


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Comment at: llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp:126
+  unsigned reg = fieldFromInstruction(Insn, 4, 5);
+  if (DecodeGPR8RegisterClass(Inst, reg, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+  Inst.addOperand(MCOperand::createImm(addr));
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Place the early return on a new line for visibility


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Comment at: llvm/test/MC/AVR/inst-cbi.s:17
 ; CHECK: cbi 0, 0                  ; encoding: [0x00,0x98]
 ; CHECK: cbi 7, 2                  ; encoding: [0x3a,0x98]
 
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Add a couple instructions that exercise all the instruction bits, so that all bitshifts and masks are exercised

for example, `cbi 31, 7`, which should correspond to A=11111 and b=111, the max according to the datasheet.


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Comment at: llvm/test/MC/AVR/inst-in.s:23
+; CHECK-INST: in r2, 4
+; CHECK-INST: in r9, 6
+; CHECK-INST: in r5, 32
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Add a test for `in r31, 63` to exercise all the bits


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Comment at: llvm/test/MC/AVR/inst-out.s:24
+; CHECK-INST: out 6,  r9
+; CHECK-INST: out 32, r5
+; CHECK-INST: out 0,  r0
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Add a test for `out 63, r31` to exercise all the bits


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Comment at: llvm/test/MC/AVR/inst-sbi.s:23
+; CHECK-INST: sbi 3, 5
+; CHECK-INST: sbi 1, 1
+; CHECK-INST: sbi 0, 0
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Add test for `sbi 31, 7`


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Comment at: llvm/test/MC/AVR/inst-sbic.s:22
+
+; CHECK-INST: sbic 4,  3
+; CHECK-INST: sbic 6,  2
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Add test for `sbic 31, 7`


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Comment at: llvm/test/MC/AVR/inst-sbis.s:22
+; CHECK-INST: sbis 4,  3
+; CHECK-INST: sbis 6,  2
+; CHECK-INST: sbis 16, 5
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Add test for `sbis 31, 7`

 


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74049/new/

https://reviews.llvm.org/D74049