[PATCH] D74254: [llvm][aarch64] SVE addressing modes.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen accepted this revision.
sdesmalen added a comment.
This revision is now accepted and ready to land.

LGTM!



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:4473
+  const SDValue ShiftRHS = RHS.getOperand(1);
+  auto *C = dyn_cast<ConstantSDNode>(ShiftRHS);
+  if (nullptr == C)
----------------
```if (auto *C = dyn_cast<ConstantSDNode>(ShiftRHS)) {
  if (ShiftAmount == C->getZExtValue()) {
    ...
    return true;
  }
}

return false;```


================
Comment at: llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll:250
+                                      <vscale x 2 x i8> *%base_load,
+                                      i32 8,
+                                      <vscale x 2 x i1> %mask)
----------------
nit: did you chose a different alignment here on purpose?


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  https://reviews.llvm.org/D74254/new/

https://reviews.llvm.org/D74254