[PATCH] D74858: [AArch64][SVE] Add intrinsics for non-temporal gather-loads/scatter-stores

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added a comment.

This patch is doing a lot of refactoring/renaming, can you separate that out into a separate NFC patch?
On the point for having separate intrinsics for (vector, scalar) and (scalar, vector), I think this makes sense, as we'll then use similar intrinsics for ldnt1 and ld1 and we can target the right instruction in a similar way we do this in `performLD1GatherCombine`.



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Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:1266
+
+def int_aarch64_sve_ldnt1_gather : SVE2_NTGatherLoad_VectorBase_Intrinsic;
+def int_aarch64_sve_stnt1_scatter : SVE2_NTScatterStore_VectorBase_Intrinsic;
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Can you derive from AdvSIMD_GatherLoad_VectorBase_Intrinsic instead?
(and something similar for the scatter store)

This also makes it more clear that these have the exact same form as the normal gathers.


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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:4947
 
-multiclass sve2_mem_sstnt_vs<bits<3> opc, string asm,
-                             RegisterOperand listty, ZPRRegOp zprty> {
-  def _REAL : sve2_mem_sstnt_vs_base<opc, asm, listty, zprty>;
+multiclass sve2_mem_sstnt_32b_ptrs<bits<3> opc, string asm,
+                             SDPatternOperator op,
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nit: vec_32b_ptrs ?


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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:4950
+                             ValueType vt> {
+  def _REAL : sve2_mem_sstnt_vs_base<opc, asm, Z_s, ZPR32>;
 
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If you change the name of this class, you may want to update the parent class as well.


Repository:
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https://reviews.llvm.org/D74858