[llvm] e27b61c - [XCore] Add instruction pattern for bitrev

[Jim Lin via llvm-commits]

Author: Jim Lin
Date: 2020-02-21T09:28:49+08:00
New Revision: e27b61c1ea3dbc8329673003e16ecba96600933a

URL: https://github.com/llvm/llvm-project/commit/e27b61c1ea3dbc8329673003e16ecba96600933a
DIFF: https://github.com/llvm/llvm-project/commit/e27b61c1ea3dbc8329673003e16ecba96600933a.diff

LOG: [XCore] Add instruction pattern for bitrev

Summary:
Add support for lowering bitreverse to the bitrev instruction.
Fix https://bugs.llvm.org/show_bug.cgi?id=34628.

Reviewers: RKSimon, rtrieu, robertlytton

Reviewed By: RKSimon

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74748

Added: 
    llvm/test/CodeGen/XCore/bitrev.ll

Modified: 
    llvm/lib/Target/XCore/XCoreISelLowering.cpp
    llvm/lib/Target/XCore/XCoreInstrInfo.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/llvm/lib/Target/XCore/XCoreISelLowering.cpp
index 07485586bfff..4a3944c471a1 100644
--- a/llvm/lib/Target/XCore/XCoreISelLowering.cpp
+++ b/llvm/lib/Target/XCore/XCoreISelLowering.cpp
@@ -107,6 +107,7 @@ XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::CTPOP, MVT::i32, Expand);
   setOperationAction(ISD::ROTL , MVT::i32, Expand);
   setOperationAction(ISD::ROTR , MVT::i32, Expand);
+  setOperationAction(ISD::BITREVERSE , MVT::i32, Legal);
 
   setOperationAction(ISD::TRAP, MVT::Other, Legal);
 

diff  --git a/llvm/lib/Target/XCore/XCoreInstrInfo.td b/llvm/lib/Target/XCore/XCoreInstrInfo.td
index 250314c506a7..aa3739d0335e 100644
--- a/llvm/lib/Target/XCore/XCoreInstrInfo.td
+++ b/llvm/lib/Target/XCore/XCoreInstrInfo.td
@@ -1154,6 +1154,9 @@ def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)),
 def : Pat<(store GRRegs:$val, GRRegs:$addr),
           (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>;
 
+/// bitrev
+def : Pat<(bitreverse GRRegs:$src), (BITREV_l2r GRRegs:$src)>;
+
 /// cttz
 def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>;
 

diff  --git a/llvm/test/CodeGen/XCore/bitrev.ll b/llvm/test/CodeGen/XCore/bitrev.ll
new file mode 100644
index 000000000000..0d0b4d274080
--- /dev/null
+++ b/llvm/test/CodeGen/XCore/bitrev.ll
@@ -0,0 +1,55 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -march=xcore | FileCheck %s
+
+declare i8 @llvm.bitreverse.i8(i8)
+declare i16 @llvm.bitreverse.i16(i16)
+declare i32 @llvm.bitreverse.i32(i32)
+declare i64 @llvm.bitreverse.i64(i64)
+
+define i8 @bitrev8(i8 %x) nounwind {
+; CHECK-LABEL: bitrev8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    bitrev r0, r0
+; CHECK-NEXT:    shr r0, r0, 24
+; CHECK-NEXT:    retsp 0
+; CHECK-NEXT:    .cc_bottom bitrev8.function
+entry:
+  %0 = call i8 @llvm.bitreverse.i8(i8 %x)
+  ret i8 %0
+}
+
+define i16 @bitrev16(i16 %x) nounwind {
+; CHECK-LABEL: bitrev16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    bitrev r0, r0
+; CHECK-NEXT:    shr r0, r0, 16
+; CHECK-NEXT:    retsp 0
+; CHECK-NEXT:    .cc_bottom bitrev16.function
+entry:
+  %0 = call i16 @llvm.bitreverse.i16(i16 %x)
+  ret i16 %0
+}
+
+define i32 @bitrev32(i32 %x) nounwind {
+; CHECK-LABEL: bitrev32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    bitrev r0, r0
+; CHECK-NEXT:    retsp 0
+; CHECK-NEXT:    .cc_bottom bitrev32.function
+entry:
+  %0 = call i32 @llvm.bitreverse.i32(i32 %x)
+  ret i32 %0
+}
+
+define i64 @bitrev64(i64 %x) nounwind {
+; CHECK-LABEL: bitrev64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    bitrev r2, r1
+; CHECK-NEXT:    bitrev r1, r0
+; CHECK-NEXT:    mov r0, r2
+; CHECK-NEXT:    retsp 0
+; CHECK-NEXT:    .cc_bottom bitrev64.function
+entry:
+  %0 = call i64 @llvm.bitreverse.i64(i64 %x)
+  ret i64 %0
+}