[PATCH] D74874: [mlir][spirv] Add lowering for load/store zero-rank memref from std to SPIR-V.

[Mahesh Ravishankar via Phabricator via llvm-commits]

mravishankar requested changes to this revision.
mravishankar added a comment.
This revision now requires changes to proceed.

Might be worth checking that the serialization/deserialization works as well



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Comment at: mlir/test/Conversion/StandardToSPIRV/std-to-spirv.mlir:319
+func @load_store_zero_rank_float(%arg0: memref<f32>, %arg1: memref<f32>) {
+  // CHECK: spv.AccessChain
+  // CHECK: spv.Load
----------------
Would be good to check the indices here to make sure it is doing spv.AccessChain %arg0[0]


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  https://reviews.llvm.org/D74874/new/

https://reviews.llvm.org/D74874