[llvm] 216a6e0 - [x86] regenerate test checks with less shuffle scrubbing; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 20 07:34:11 PST 2020
Author: Sanjay Patel
Date: 2020-02-20T10:34:04-05:00
New Revision: 216a6e05249544db4c1c3f30944aba3da7463eef
URL: https://github.com/llvm/llvm-project/commit/216a6e05249544db4c1c3f30944aba3da7463eef
DIFF: https://github.com/llvm/llvm-project/commit/216a6e05249544db4c1c3f30944aba3da7463eef.diff
LOG: [x86] regenerate test checks with less shuffle scrubbing; NFC
For shuffles with memory operands, we generally don't want to
hide the asm because we want to verify that the address offsets
are as expected.
Added:
Modified:
llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
llvm/test/CodeGen/X86/masked_gather.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll b/llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
index 0270fe47637f..198694a30143 100644
--- a/llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
+++ b/llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
@@ -1050,7 +1050,7 @@ define <4 x i32> @test_8xi32_to_4xi32_perm_mem_mask0(<8 x i32>* %vp) {
; CHECK-LABEL: test_8xi32_to_4xi32_perm_mem_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps 16(%rdi), %xmm0
-; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,1],mem[0,0]
+; CHECK-NEXT: vshufps $7, (%rdi), %xmm0, %xmm0 # xmm0 = xmm0[3,1],mem[0,0]
; CHECK-NEXT: retq
%vec = load <8 x i32>, <8 x i32>* %vp
%res = shufflevector <8 x i32> %vec, <8 x i32> undef, <4 x i32> <i32 7, i32 5, i32 0, i32 0>
@@ -1060,7 +1060,7 @@ define <4 x i32> @test_masked_8xi32_to_4xi32_perm_mem_mask0(<8 x i32>* %vp, <4 x
; CHECK-LABEL: test_masked_8xi32_to_4xi32_perm_mem_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps 16(%rdi), %xmm2
-; CHECK-NEXT: vshufps {{.*#+}} xmm2 = xmm2[3,1],mem[0,0]
+; CHECK-NEXT: vshufps $7, (%rdi), %xmm2, %xmm2 # xmm2 = xmm2[3,1],mem[0,0]
; CHECK-NEXT: vptestnmd %xmm1, %xmm1, %k1
; CHECK-NEXT: vmovdqa32 %xmm2, %xmm0 {%k1}
; CHECK-NEXT: retq
@@ -1075,7 +1075,7 @@ define <4 x i32> @test_masked_z_8xi32_to_4xi32_perm_mem_mask0(<8 x i32>* %vp, <4
; CHECK-LABEL: test_masked_z_8xi32_to_4xi32_perm_mem_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps 16(%rdi), %xmm1
-; CHECK-NEXT: vshufps {{.*#+}} xmm1 = xmm1[3,1],mem[0,0]
+; CHECK-NEXT: vshufps $7, (%rdi), %xmm1, %xmm1 # xmm1 = xmm1[3,1],mem[0,0]
; CHECK-NEXT: vptestnmd %xmm0, %xmm0, %k1
; CHECK-NEXT: vmovdqa32 %xmm1, %xmm0 {%k1} {z}
; CHECK-NEXT: retq
@@ -1868,7 +1868,7 @@ define <2 x i64> @test_4xi64_to_2xi64_perm_mem_mask0(<4 x i64>* %vp) {
; CHECK-LABEL: test_4xi64_to_2xi64_perm_mem_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps (%rdi), %xmm0
-; CHECK-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],mem[1]
+; CHECK-NEXT: vunpckhpd 16(%rdi), %xmm0, %xmm0 # xmm0 = xmm0[1],mem[1]
; CHECK-NEXT: retq
%vec = load <4 x i64>, <4 x i64>* %vp
%res = shufflevector <4 x i64> %vec, <4 x i64> undef, <2 x i32> <i32 1, i32 3>
@@ -1879,7 +1879,7 @@ define <2 x i64> @test_masked_4xi64_to_2xi64_perm_mem_mask0(<4 x i64>* %vp, <2 x
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa (%rdi), %xmm2
; CHECK-NEXT: vptestnmq %xmm1, %xmm1, %k1
-; CHECK-NEXT: vpunpckhqdq {{.*#+}} xmm0 {%k1} = xmm2[1],mem[1]
+; CHECK-NEXT: vpunpckhqdq 16(%rdi), %xmm2, %xmm0 {%k1} # xmm0 {%k1} = xmm2[1],mem[1]
; CHECK-NEXT: retq
%vec = load <4 x i64>, <4 x i64>* %vp
%shuf = shufflevector <4 x i64> %vec, <4 x i64> undef, <2 x i32> <i32 1, i32 3>
@@ -1893,7 +1893,7 @@ define <2 x i64> @test_masked_z_4xi64_to_2xi64_perm_mem_mask0(<4 x i64>* %vp, <2
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa (%rdi), %xmm1
; CHECK-NEXT: vptestnmq %xmm0, %xmm0, %k1
-; CHECK-NEXT: vpunpckhqdq {{.*#+}} xmm0 {%k1} {z} = xmm1[1],mem[1]
+; CHECK-NEXT: vpunpckhqdq 16(%rdi), %xmm1, %xmm0 {%k1} {z} # xmm0 {%k1} {z} = xmm1[1],mem[1]
; CHECK-NEXT: retq
%vec = load <4 x i64>, <4 x i64>* %vp
%shuf = shufflevector <4 x i64> %vec, <4 x i64> undef, <2 x i32> <i32 1, i32 3>
@@ -1906,7 +1906,7 @@ define <2 x i64> @test_masked_4xi64_to_2xi64_perm_mem_mask1(<4 x i64>* %vp, <2 x
; CHECK-LABEL: test_masked_4xi64_to_2xi64_perm_mem_mask1:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa 16(%rdi), %xmm2
-; CHECK-NEXT: vpblendd {{.*#+}} xmm2 = xmm2[0,1],mem[2,3]
+; CHECK-NEXT: vpblendd $12, (%rdi), %xmm2, %xmm2 # xmm2 = xmm2[0,1],mem[2,3]
; CHECK-NEXT: vptestnmq %xmm1, %xmm1, %k1
; CHECK-NEXT: vmovdqa64 %xmm2, %xmm0 {%k1}
; CHECK-NEXT: retq
@@ -1921,7 +1921,7 @@ define <2 x i64> @test_masked_z_4xi64_to_2xi64_perm_mem_mask1(<4 x i64>* %vp, <2
; CHECK-LABEL: test_masked_z_4xi64_to_2xi64_perm_mem_mask1:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa 16(%rdi), %xmm1
-; CHECK-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0,1],mem[2,3]
+; CHECK-NEXT: vpblendd $12, (%rdi), %xmm1, %xmm1 # xmm1 = xmm1[0,1],mem[2,3]
; CHECK-NEXT: vptestnmq %xmm0, %xmm0, %k1
; CHECK-NEXT: vmovdqa64 %xmm1, %xmm0 {%k1} {z}
; CHECK-NEXT: retq
@@ -2256,7 +2256,7 @@ define <2 x i64> @test_masked_z_8xi64_to_2xi64_perm_mask1(<8 x i64> %vec, <2 x i
define <4 x i64> @test_8xi64_to_4xi64_perm_mem_mask0(<8 x i64>* %vp) {
; CHECK-LABEL: test_8xi64_to_4xi64_perm_mem_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpermpd {{.*#+}} ymm0 = mem[0,2,0,2]
+; CHECK-NEXT: vpermpd $136, (%rdi), %ymm0 # ymm0 = mem[0,2,0,2]
; CHECK-NEXT: retq
%vec = load <8 x i64>, <8 x i64>* %vp
%res = shufflevector <8 x i64> %vec, <8 x i64> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
@@ -2266,7 +2266,7 @@ define <4 x i64> @test_masked_8xi64_to_4xi64_perm_mem_mask0(<8 x i64>* %vp, <4 x
; CHECK-LABEL: test_masked_8xi64_to_4xi64_perm_mem_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: vptestnmq %ymm1, %ymm1, %k1
-; CHECK-NEXT: vpermq {{.*#+}} ymm0 {%k1} = mem[0,2,0,2]
+; CHECK-NEXT: vpermq $136, (%rdi), %ymm0 {%k1} # ymm0 {%k1} = mem[0,2,0,2]
; CHECK-NEXT: retq
%vec = load <8 x i64>, <8 x i64>* %vp
%shuf = shufflevector <8 x i64> %vec, <8 x i64> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
@@ -2279,7 +2279,7 @@ define <4 x i64> @test_masked_z_8xi64_to_4xi64_perm_mem_mask0(<8 x i64>* %vp, <4
; CHECK-LABEL: test_masked_z_8xi64_to_4xi64_perm_mem_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: vptestnmq %ymm0, %ymm0, %k1
-; CHECK-NEXT: vpermq {{.*#+}} ymm0 {%k1} {z} = mem[0,2,0,2]
+; CHECK-NEXT: vpermq $136, (%rdi), %ymm0 {%k1} {z} # ymm0 {%k1} {z} = mem[0,2,0,2]
; CHECK-NEXT: retq
%vec = load <8 x i64>, <8 x i64>* %vp
%shuf = shufflevector <8 x i64> %vec, <8 x i64> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
@@ -2538,7 +2538,7 @@ define <2 x i64> @test_8xi64_to_2xi64_perm_mem_mask0(<8 x i64>* %vp) {
; CHECK-LABEL: test_8xi64_to_2xi64_perm_mem_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps 32(%rdi), %xmm0
-; CHECK-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],mem[2,3]
+; CHECK-NEXT: vblendps $12, (%rdi), %xmm0, %xmm0 # xmm0 = xmm0[0,1],mem[2,3]
; CHECK-NEXT: retq
%vec = load <8 x i64>, <8 x i64>* %vp
%res = shufflevector <8 x i64> %vec, <8 x i64> undef, <2 x i32> <i32 4, i32 1>
@@ -2548,7 +2548,7 @@ define <2 x i64> @test_masked_8xi64_to_2xi64_perm_mem_mask0(<8 x i64>* %vp, <2 x
; CHECK-LABEL: test_masked_8xi64_to_2xi64_perm_mem_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa 32(%rdi), %xmm2
-; CHECK-NEXT: vpblendd {{.*#+}} xmm2 = xmm2[0,1],mem[2,3]
+; CHECK-NEXT: vpblendd $12, (%rdi), %xmm2, %xmm2 # xmm2 = xmm2[0,1],mem[2,3]
; CHECK-NEXT: vptestnmq %xmm1, %xmm1, %k1
; CHECK-NEXT: vmovdqa64 %xmm2, %xmm0 {%k1}
; CHECK-NEXT: retq
@@ -2563,7 +2563,7 @@ define <2 x i64> @test_masked_z_8xi64_to_2xi64_perm_mem_mask0(<8 x i64>* %vp, <2
; CHECK-LABEL: test_masked_z_8xi64_to_2xi64_perm_mem_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa 32(%rdi), %xmm1
-; CHECK-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0,1],mem[2,3]
+; CHECK-NEXT: vpblendd $12, (%rdi), %xmm1, %xmm1 # xmm1 = xmm1[0,1],mem[2,3]
; CHECK-NEXT: vptestnmq %xmm0, %xmm0, %k1
; CHECK-NEXT: vmovdqa64 %xmm1, %xmm0 {%k1} {z}
; CHECK-NEXT: retq
@@ -2578,7 +2578,7 @@ define <2 x i64> @test_masked_8xi64_to_2xi64_perm_mem_mask1(<8 x i64>* %vp, <2 x
; CHECK-LABEL: test_masked_8xi64_to_2xi64_perm_mem_mask1:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa 32(%rdi), %ymm2
-; CHECK-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm2[0],mem[0],ymm2[2],mem[2]
+; CHECK-NEXT: vpunpcklqdq (%rdi), %ymm2, %ymm2 # ymm2 = ymm2[0],mem[0],ymm2[2],mem[2]
; CHECK-NEXT: vextracti128 $1, %ymm2, %xmm2
; CHECK-NEXT: vptestnmq %xmm1, %xmm1, %k1
; CHECK-NEXT: vmovdqa64 %xmm2, %xmm0 {%k1}
@@ -2595,7 +2595,7 @@ define <2 x i64> @test_masked_z_8xi64_to_2xi64_perm_mem_mask1(<8 x i64>* %vp, <2
; CHECK-LABEL: test_masked_z_8xi64_to_2xi64_perm_mem_mask1:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa 32(%rdi), %ymm1
-; CHECK-NEXT: vpunpcklqdq {{.*#+}} ymm1 = ymm1[0],mem[0],ymm1[2],mem[2]
+; CHECK-NEXT: vpunpcklqdq (%rdi), %ymm1, %ymm1 # ymm1 = ymm1[0],mem[0],ymm1[2],mem[2]
; CHECK-NEXT: vextracti128 $1, %ymm1, %xmm1
; CHECK-NEXT: vptestnmq %xmm0, %xmm0, %k1
; CHECK-NEXT: vmovdqa64 %xmm1, %xmm0 {%k1} {z}
@@ -3359,7 +3359,7 @@ define <8 x float> @test_masked_z_16xfloat_to_8xfloat_perm_mem_mask3(<16 x float
define <4 x float> @test_16xfloat_to_4xfloat_perm_mem_mask0(<16 x float>* %vp) {
; CHECK-LABEL: test_16xfloat_to_4xfloat_perm_mem_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpermpd {{.*#+}} ymm1 = mem[3,1,2,3]
+; CHECK-NEXT: vpermpd $231, 32(%rdi), %ymm1 # ymm1 = mem[3,1,2,3]
; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [0,6,7,3]
; CHECK-NEXT: vpermi2ps 16(%rdi), %xmm1, %xmm0
; CHECK-NEXT: vzeroupper
@@ -3371,7 +3371,7 @@ define <4 x float> @test_16xfloat_to_4xfloat_perm_mem_mask0(<16 x float>* %vp) {
define <4 x float> @test_masked_16xfloat_to_4xfloat_perm_mem_mask0(<16 x float>* %vp, <4 x float> %vec2, <4 x float> %mask) {
; CHECK-LABEL: test_masked_16xfloat_to_4xfloat_perm_mem_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpermpd {{.*#+}} ymm2 = mem[3,1,2,3]
+; CHECK-NEXT: vpermpd $231, 32(%rdi), %ymm2 # ymm2 = mem[3,1,2,3]
; CHECK-NEXT: vmovaps {{.*#+}} xmm3 = [0,6,7,3]
; CHECK-NEXT: vpermi2ps 16(%rdi), %xmm2, %xmm3
; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
@@ -3389,7 +3389,7 @@ define <4 x float> @test_masked_16xfloat_to_4xfloat_perm_mem_mask0(<16 x float>*
define <4 x float> @test_masked_z_16xfloat_to_4xfloat_perm_mem_mask0(<16 x float>* %vp, <4 x float> %mask) {
; CHECK-LABEL: test_masked_z_16xfloat_to_4xfloat_perm_mem_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpermpd {{.*#+}} ymm2 = mem[3,1,2,3]
+; CHECK-NEXT: vpermpd $231, 32(%rdi), %ymm2 # ymm2 = mem[3,1,2,3]
; CHECK-NEXT: vmovaps {{.*#+}} xmm1 = [0,6,7,3]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %xmm3, %xmm0, %k1
@@ -3597,7 +3597,7 @@ define <2 x double> @test_4xdouble_to_2xdouble_perm_mem_mask0(<4 x double>* %vp)
; CHECK-LABEL: test_4xdouble_to_2xdouble_perm_mem_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps (%rdi), %xmm0
-; CHECK-NEXT: vblendps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
+; CHECK-NEXT: vblendps $3, 16(%rdi), %xmm0, %xmm0 # xmm0 = mem[0,1],xmm0[2,3]
; CHECK-NEXT: retq
%vec = load <4 x double>, <4 x double>* %vp
%res = shufflevector <4 x double> %vec, <4 x double> undef, <2 x i32> <i32 2, i32 1>
@@ -3607,7 +3607,7 @@ define <2 x double> @test_masked_4xdouble_to_2xdouble_perm_mem_mask0(<4 x double
; CHECK-LABEL: test_masked_4xdouble_to_2xdouble_perm_mem_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovapd (%rdi), %xmm2
-; CHECK-NEXT: vblendpd {{.*#+}} xmm2 = mem[0],xmm2[1]
+; CHECK-NEXT: vblendpd $1, 16(%rdi), %xmm2, %xmm2 # xmm2 = mem[0],xmm2[1]
; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqpd %xmm3, %xmm1, %k1
; CHECK-NEXT: vmovapd %xmm2, %xmm0 {%k1}
@@ -3623,7 +3623,7 @@ define <2 x double> @test_masked_z_4xdouble_to_2xdouble_perm_mem_mask0(<4 x doub
; CHECK-LABEL: test_masked_z_4xdouble_to_2xdouble_perm_mem_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovapd (%rdi), %xmm1
-; CHECK-NEXT: vblendpd {{.*#+}} xmm1 = mem[0],xmm1[1]
+; CHECK-NEXT: vblendpd $1, 16(%rdi), %xmm1, %xmm1 # xmm1 = mem[0],xmm1[1]
; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqpd %xmm2, %xmm0, %k1
; CHECK-NEXT: vmovapd %xmm1, %xmm0 {%k1} {z}
@@ -3641,7 +3641,7 @@ define <2 x double> @test_masked_4xdouble_to_2xdouble_perm_mem_mask1(<4 x double
; CHECK-NEXT: vmovapd 16(%rdi), %xmm2
; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqpd %xmm3, %xmm1, %k1
-; CHECK-NEXT: vunpcklpd {{.*#+}} xmm0 {%k1} = xmm2[0],mem[0]
+; CHECK-NEXT: vunpcklpd (%rdi), %xmm2, %xmm0 {%k1} # xmm0 {%k1} = xmm2[0],mem[0]
; CHECK-NEXT: retq
%vec = load <4 x double>, <4 x double>* %vp
%shuf = shufflevector <4 x double> %vec, <4 x double> undef, <2 x i32> <i32 2, i32 0>
@@ -3656,7 +3656,7 @@ define <2 x double> @test_masked_z_4xdouble_to_2xdouble_perm_mem_mask1(<4 x doub
; CHECK-NEXT: vmovapd 16(%rdi), %xmm1
; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqpd %xmm2, %xmm0, %k1
-; CHECK-NEXT: vunpcklpd {{.*#+}} xmm0 {%k1} {z} = xmm1[0],mem[0]
+; CHECK-NEXT: vunpcklpd (%rdi), %xmm1, %xmm0 {%k1} {z} # xmm0 {%k1} {z} = xmm1[0],mem[0]
; CHECK-NEXT: retq
%vec = load <4 x double>, <4 x double>* %vp
%shuf = shufflevector <4 x double> %vec, <4 x double> undef, <2 x i32> <i32 2, i32 0>
@@ -4206,7 +4206,7 @@ define <4 x double> @test_masked_8xdouble_to_4xdouble_perm_mem_mask5(<8 x double
; CHECK-LABEL: test_masked_8xdouble_to_4xdouble_perm_mem_mask5:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovapd (%rdi), %ymm2
-; CHECK-NEXT: vperm2f128 {{.*#+}} ymm2 = ymm2[2,3],mem[0,1]
+; CHECK-NEXT: vperm2f128 $33, 32(%rdi), %ymm2, %ymm2 # ymm2 = ymm2[2,3],mem[0,1]
; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqpd %ymm3, %ymm1, %k1
; CHECK-NEXT: vshufpd $14, 40(%rdi){1to4}, %ymm2, %ymm0 {%k1}
@@ -4222,7 +4222,7 @@ define <4 x double> @test_masked_z_8xdouble_to_4xdouble_perm_mem_mask5(<8 x doub
; CHECK-LABEL: test_masked_z_8xdouble_to_4xdouble_perm_mem_mask5:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovapd (%rdi), %ymm1
-; CHECK-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm1[2,3],mem[0,1]
+; CHECK-NEXT: vperm2f128 $33, 32(%rdi), %ymm1, %ymm1 # ymm1 = ymm1[2,3],mem[0,1]
; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqpd %ymm2, %ymm0, %k1
; CHECK-NEXT: vshufpd $14, 40(%rdi){1to4}, %ymm1, %ymm0 {%k1} {z}
@@ -4283,7 +4283,7 @@ define <4 x double> @test_masked_8xdouble_to_4xdouble_perm_mem_mask7(<8 x double
; CHECK-LABEL: test_masked_8xdouble_to_4xdouble_perm_mem_mask7:
; CHECK: # %bb.0:
; CHECK-NEXT: vbroadcastsd 40(%rdi), %ymm2
-; CHECK-NEXT: vblendpd {{.*#+}} ymm2 = mem[0],ymm2[1],mem[2],ymm2[3]
+; CHECK-NEXT: vblendpd $5, (%rdi), %ymm2, %ymm2 # ymm2 = mem[0],ymm2[1],mem[2],ymm2[3]
; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqpd %ymm3, %ymm1, %k1
; CHECK-NEXT: vmovapd %ymm2, %ymm0 {%k1}
@@ -4299,7 +4299,7 @@ define <4 x double> @test_masked_z_8xdouble_to_4xdouble_perm_mem_mask7(<8 x doub
; CHECK-LABEL: test_masked_z_8xdouble_to_4xdouble_perm_mem_mask7:
; CHECK: # %bb.0:
; CHECK-NEXT: vbroadcastsd 40(%rdi), %ymm1
-; CHECK-NEXT: vblendpd {{.*#+}} ymm1 = mem[0],ymm1[1],mem[2],ymm1[3]
+; CHECK-NEXT: vblendpd $5, (%rdi), %ymm1, %ymm1 # ymm1 = mem[0],ymm1[1],mem[2],ymm1[3]
; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqpd %ymm2, %ymm0, %k1
; CHECK-NEXT: vmovapd %ymm1, %ymm0 {%k1} {z}
@@ -4315,7 +4315,7 @@ define <2 x double> @test_8xdouble_to_2xdouble_perm_mem_mask0(<8 x double>* %vp)
; CHECK-LABEL: test_8xdouble_to_2xdouble_perm_mem_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovapd (%rdi), %xmm0
-; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1],mem[0]
+; CHECK-NEXT: vshufpd $1, 48(%rdi), %xmm0, %xmm0 # xmm0 = xmm0[1],mem[0]
; CHECK-NEXT: retq
%vec = load <8 x double>, <8 x double>* %vp
%res = shufflevector <8 x double> %vec, <8 x double> undef, <2 x i32> <i32 1, i32 6>
@@ -4327,7 +4327,7 @@ define <2 x double> @test_masked_8xdouble_to_2xdouble_perm_mem_mask0(<8 x double
; CHECK-NEXT: vmovapd (%rdi), %xmm2
; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqpd %xmm3, %xmm1, %k1
-; CHECK-NEXT: vshufpd {{.*#+}} xmm0 {%k1} = xmm2[1],mem[0]
+; CHECK-NEXT: vshufpd $1, 48(%rdi), %xmm2, %xmm0 {%k1} # xmm0 {%k1} = xmm2[1],mem[0]
; CHECK-NEXT: retq
%vec = load <8 x double>, <8 x double>* %vp
%shuf = shufflevector <8 x double> %vec, <8 x double> undef, <2 x i32> <i32 1, i32 6>
@@ -4342,7 +4342,7 @@ define <2 x double> @test_masked_z_8xdouble_to_2xdouble_perm_mem_mask0(<8 x doub
; CHECK-NEXT: vmovapd (%rdi), %xmm1
; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqpd %xmm2, %xmm0, %k1
-; CHECK-NEXT: vshufpd {{.*#+}} xmm0 {%k1} {z} = xmm1[1],mem[0]
+; CHECK-NEXT: vshufpd $1, 48(%rdi), %xmm1, %xmm0 {%k1} {z} # xmm0 {%k1} {z} = xmm1[1],mem[0]
; CHECK-NEXT: retq
%vec = load <8 x double>, <8 x double>* %vp
%shuf = shufflevector <8 x double> %vec, <8 x double> undef, <2 x i32> <i32 1, i32 6>
@@ -4392,7 +4392,7 @@ define <2 x double> @test_masked_z_8xdouble_to_2xdouble_perm_mem_mask1(<8 x doub
define void @test_zext_v8i8_to_v8i16(<8 x i8>* %arg, <8 x i16>* %arg1) {
; CHECK-LABEL: test_zext_v8i8_to_v8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
+; CHECK-NEXT: vmovq (%rdi), %xmm0 # xmm0 = mem[0],zero
; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
; CHECK-NEXT: vmovdqa %xmm0, (%rsi)
diff --git a/llvm/test/CodeGen/X86/masked_gather.ll b/llvm/test/CodeGen/X86/masked_gather.ll
index 7ea2cacd77b1..138b33d55b6a 100644
--- a/llvm/test/CodeGen/X86/masked_gather.ll
+++ b/llvm/test/CodeGen/X86/masked_gather.ll
@@ -34,23 +34,23 @@ define <4 x float> @gather_v4f32_ptr_v4i32(<4 x float*> %ptr, <4 x i32> %trigger
; SSE-NEXT: retq
; SSE-NEXT: .LBB0_1: # %cond.load
; SSE-NEXT: movq %xmm0, %rcx
-; SSE-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; SSE-NEXT: movd (%rcx), %xmm2 # xmm2 = mem[0],zero,zero,zero
; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm2[0,1],xmm3[2,3,4,5,6,7]
; SSE-NEXT: testb $2, %al
; SSE-NEXT: je .LBB0_4
; SSE-NEXT: .LBB0_3: # %cond.load1
; SSE-NEXT: pextrq $1, %xmm0, %rcx
-; SSE-NEXT: insertps {{.*#+}} xmm3 = xmm3[0],mem[0],xmm3[2,3]
+; SSE-NEXT: insertps $16, (%rcx), %xmm3 # xmm3 = xmm3[0],mem[0],xmm3[2,3]
; SSE-NEXT: testb $4, %al
; SSE-NEXT: je .LBB0_6
; SSE-NEXT: .LBB0_5: # %cond.load4
; SSE-NEXT: movq %xmm1, %rcx
-; SSE-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1],mem[0],xmm3[3]
+; SSE-NEXT: insertps $32, (%rcx), %xmm3 # xmm3 = xmm3[0,1],mem[0],xmm3[3]
; SSE-NEXT: testb $8, %al
; SSE-NEXT: je .LBB0_8
; SSE-NEXT: .LBB0_7: # %cond.load7
; SSE-NEXT: pextrq $1, %xmm1, %rax
-; SSE-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1,2],mem[0]
+; SSE-NEXT: insertps $48, (%rax), %xmm3 # xmm3 = xmm3[0,1,2],mem[0]
; SSE-NEXT: movaps %xmm3, %xmm0
; SSE-NEXT: retq
;
@@ -63,14 +63,14 @@ define <4 x float> @gather_v4f32_ptr_v4i32(<4 x float*> %ptr, <4 x i32> %trigger
; AVX1-NEXT: je .LBB0_2
; AVX1-NEXT: # %bb.1: # %cond.load
; AVX1-NEXT: vmovq %xmm0, %rcx
-; AVX1-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; AVX1-NEXT: vmovss (%rcx), %xmm1 # xmm1 = mem[0],zero,zero,zero
; AVX1-NEXT: vblendps {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; AVX1-NEXT: .LBB0_2: # %else
; AVX1-NEXT: testb $2, %al
; AVX1-NEXT: je .LBB0_4
; AVX1-NEXT: # %bb.3: # %cond.load1
; AVX1-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3]
+; AVX1-NEXT: vinsertps $16, (%rcx), %xmm2, %xmm2 # xmm2 = xmm2[0],mem[0],xmm2[2,3]
; AVX1-NEXT: .LBB0_4: # %else2
; AVX1-NEXT: testb $4, %al
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
@@ -84,12 +84,12 @@ define <4 x float> @gather_v4f32_ptr_v4i32(<4 x float*> %ptr, <4 x i32> %trigger
; AVX1-NEXT: retq
; AVX1-NEXT: .LBB0_5: # %cond.load4
; AVX1-NEXT: vmovq %xmm0, %rcx
-; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3]
+; AVX1-NEXT: vinsertps $32, (%rcx), %xmm2, %xmm2 # xmm2 = xmm2[0,1],mem[0],xmm2[3]
; AVX1-NEXT: testb $8, %al
; AVX1-NEXT: je .LBB0_8
; AVX1-NEXT: .LBB0_7: # %cond.load7
; AVX1-NEXT: vpextrq $1, %xmm0, %rax
-; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0]
+; AVX1-NEXT: vinsertps $48, (%rax), %xmm2, %xmm2 # xmm2 = xmm2[0,1,2],mem[0]
; AVX1-NEXT: vmovaps %xmm2, %xmm0
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
@@ -103,14 +103,14 @@ define <4 x float> @gather_v4f32_ptr_v4i32(<4 x float*> %ptr, <4 x i32> %trigger
; AVX2-NEXT: je .LBB0_2
; AVX2-NEXT: # %bb.1: # %cond.load
; AVX2-NEXT: vmovq %xmm0, %rcx
-; AVX2-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; AVX2-NEXT: vmovss (%rcx), %xmm1 # xmm1 = mem[0],zero,zero,zero
; AVX2-NEXT: vblendps {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; AVX2-NEXT: .LBB0_2: # %else
; AVX2-NEXT: testb $2, %al
; AVX2-NEXT: je .LBB0_4
; AVX2-NEXT: # %bb.3: # %cond.load1
; AVX2-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3]
+; AVX2-NEXT: vinsertps $16, (%rcx), %xmm2, %xmm2 # xmm2 = xmm2[0],mem[0],xmm2[2,3]
; AVX2-NEXT: .LBB0_4: # %else2
; AVX2-NEXT: testb $4, %al
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
@@ -124,12 +124,12 @@ define <4 x float> @gather_v4f32_ptr_v4i32(<4 x float*> %ptr, <4 x i32> %trigger
; AVX2-NEXT: retq
; AVX2-NEXT: .LBB0_5: # %cond.load4
; AVX2-NEXT: vmovq %xmm0, %rcx
-; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3]
+; AVX2-NEXT: vinsertps $32, (%rcx), %xmm2, %xmm2 # xmm2 = xmm2[0,1],mem[0],xmm2[3]
; AVX2-NEXT: testb $8, %al
; AVX2-NEXT: je .LBB0_8
; AVX2-NEXT: .LBB0_7: # %cond.load7
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
-; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0]
+; AVX2-NEXT: vinsertps $48, (%rax), %xmm2, %xmm2 # xmm2 = xmm2[0,1,2],mem[0]
; AVX2-NEXT: vmovaps %xmm2, %xmm0
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
@@ -168,7 +168,7 @@ define <4 x float> @gather_v4f32_v4i32_v4i32(float* %base, <4 x i32> %idx, <4 x
; SSE-NEXT: je .LBB1_2
; SSE-NEXT: # %bb.1: # %cond.load
; SSE-NEXT: movq %xmm4, %rcx
-; SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE-NEXT: movd (%rcx), %xmm1 # xmm1 = mem[0],zero,zero,zero
; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0,1],xmm2[2,3,4,5,6,7]
; SSE-NEXT: .LBB1_2: # %else
; SSE-NEXT: psllq $2, %xmm0
@@ -176,7 +176,7 @@ define <4 x float> @gather_v4f32_v4i32_v4i32(float* %base, <4 x i32> %idx, <4 x
; SSE-NEXT: je .LBB1_4
; SSE-NEXT: # %bb.3: # %cond.load1
; SSE-NEXT: pextrq $1, %xmm4, %rcx
-; SSE-NEXT: insertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3]
+; SSE-NEXT: insertps $16, (%rcx), %xmm2 # xmm2 = xmm2[0],mem[0],xmm2[2,3]
; SSE-NEXT: .LBB1_4: # %else2
; SSE-NEXT: paddq %xmm0, %xmm3
; SSE-NEXT: testb $4, %al
@@ -189,12 +189,12 @@ define <4 x float> @gather_v4f32_v4i32_v4i32(float* %base, <4 x i32> %idx, <4 x
; SSE-NEXT: retq
; SSE-NEXT: .LBB1_5: # %cond.load4
; SSE-NEXT: movq %xmm3, %rcx
-; SSE-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3]
+; SSE-NEXT: insertps $32, (%rcx), %xmm2 # xmm2 = xmm2[0,1],mem[0],xmm2[3]
; SSE-NEXT: testb $8, %al
; SSE-NEXT: je .LBB1_8
; SSE-NEXT: .LBB1_7: # %cond.load7
; SSE-NEXT: pextrq $1, %xmm3, %rax
-; SSE-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0]
+; SSE-NEXT: insertps $48, (%rax), %xmm2 # xmm2 = xmm2[0,1,2],mem[0]
; SSE-NEXT: movaps %xmm2, %xmm0
; SSE-NEXT: retq
;
@@ -217,14 +217,14 @@ define <4 x float> @gather_v4f32_v4i32_v4i32(float* %base, <4 x i32> %idx, <4 x
; AVX1-NEXT: je .LBB1_2
; AVX1-NEXT: # %bb.1: # %cond.load
; AVX1-NEXT: vmovq %xmm0, %rcx
-; AVX1-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; AVX1-NEXT: vmovss (%rcx), %xmm1 # xmm1 = mem[0],zero,zero,zero
; AVX1-NEXT: vblendps {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; AVX1-NEXT: .LBB1_2: # %else
; AVX1-NEXT: testb $2, %al
; AVX1-NEXT: je .LBB1_4
; AVX1-NEXT: # %bb.3: # %cond.load1
; AVX1-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3]
+; AVX1-NEXT: vinsertps $16, (%rcx), %xmm2, %xmm2 # xmm2 = xmm2[0],mem[0],xmm2[2,3]
; AVX1-NEXT: .LBB1_4: # %else2
; AVX1-NEXT: testb $4, %al
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
@@ -238,12 +238,12 @@ define <4 x float> @gather_v4f32_v4i32_v4i32(float* %base, <4 x i32> %idx, <4 x
; AVX1-NEXT: retq
; AVX1-NEXT: .LBB1_5: # %cond.load4
; AVX1-NEXT: vmovq %xmm0, %rcx
-; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3]
+; AVX1-NEXT: vinsertps $32, (%rcx), %xmm2, %xmm2 # xmm2 = xmm2[0,1],mem[0],xmm2[3]
; AVX1-NEXT: testb $8, %al
; AVX1-NEXT: je .LBB1_8
; AVX1-NEXT: .LBB1_7: # %cond.load7
; AVX1-NEXT: vpextrq $1, %xmm0, %rax
-; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0]
+; AVX1-NEXT: vinsertps $48, (%rax), %xmm2, %xmm2 # xmm2 = xmm2[0,1,2],mem[0]
; AVX1-NEXT: vmovaps %xmm2, %xmm0
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
@@ -262,14 +262,14 @@ define <4 x float> @gather_v4f32_v4i32_v4i32(float* %base, <4 x i32> %idx, <4 x
; AVX2-NEXT: je .LBB1_2
; AVX2-NEXT: # %bb.1: # %cond.load
; AVX2-NEXT: vmovq %xmm0, %rcx
-; AVX2-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; AVX2-NEXT: vmovss (%rcx), %xmm1 # xmm1 = mem[0],zero,zero,zero
; AVX2-NEXT: vblendps {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; AVX2-NEXT: .LBB1_2: # %else
; AVX2-NEXT: testb $2, %al
; AVX2-NEXT: je .LBB1_4
; AVX2-NEXT: # %bb.3: # %cond.load1
; AVX2-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3]
+; AVX2-NEXT: vinsertps $16, (%rcx), %xmm2, %xmm2 # xmm2 = xmm2[0],mem[0],xmm2[2,3]
; AVX2-NEXT: .LBB1_4: # %else2
; AVX2-NEXT: testb $4, %al
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
@@ -283,12 +283,12 @@ define <4 x float> @gather_v4f32_v4i32_v4i32(float* %base, <4 x i32> %idx, <4 x
; AVX2-NEXT: retq
; AVX2-NEXT: .LBB1_5: # %cond.load4
; AVX2-NEXT: vmovq %xmm0, %rcx
-; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3]
+; AVX2-NEXT: vinsertps $32, (%rcx), %xmm2, %xmm2 # xmm2 = xmm2[0,1],mem[0],xmm2[3]
; AVX2-NEXT: testb $8, %al
; AVX2-NEXT: je .LBB1_8
; AVX2-NEXT: .LBB1_7: # %cond.load7
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
-; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0]
+; AVX2-NEXT: vinsertps $48, (%rax), %xmm2, %xmm2 # xmm2 = xmm2[0,1,2],mem[0]
; AVX2-NEXT: vmovaps %xmm2, %xmm0
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
@@ -328,7 +328,7 @@ define <4 x float> @gather_v4f32_v4i64_v4i32(float* %base, <4 x i64> %idx, <4 x
; SSE-NEXT: je .LBB2_2
; SSE-NEXT: # %bb.1: # %cond.load
; SSE-NEXT: movq %xmm0, %rcx
-; SSE-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; SSE-NEXT: movd (%rcx), %xmm2 # xmm2 = mem[0],zero,zero,zero
; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm2[0,1],xmm3[2,3,4,5,6,7]
; SSE-NEXT: .LBB2_2: # %else
; SSE-NEXT: psllq $2, %xmm1
@@ -336,7 +336,7 @@ define <4 x float> @gather_v4f32_v4i64_v4i32(float* %base, <4 x i64> %idx, <4 x
; SSE-NEXT: je .LBB2_4
; SSE-NEXT: # %bb.3: # %cond.load1
; SSE-NEXT: pextrq $1, %xmm0, %rcx
-; SSE-NEXT: insertps {{.*#+}} xmm3 = xmm3[0],mem[0],xmm3[2,3]
+; SSE-NEXT: insertps $16, (%rcx), %xmm3 # xmm3 = xmm3[0],mem[0],xmm3[2,3]
; SSE-NEXT: .LBB2_4: # %else2
; SSE-NEXT: paddq %xmm1, %xmm4
; SSE-NEXT: testb $4, %al
@@ -349,12 +349,12 @@ define <4 x float> @gather_v4f32_v4i64_v4i32(float* %base, <4 x i64> %idx, <4 x
; SSE-NEXT: retq
; SSE-NEXT: .LBB2_5: # %cond.load4
; SSE-NEXT: movq %xmm4, %rcx
-; SSE-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1],mem[0],xmm3[3]
+; SSE-NEXT: insertps $32, (%rcx), %xmm3 # xmm3 = xmm3[0,1],mem[0],xmm3[3]
; SSE-NEXT: testb $8, %al
; SSE-NEXT: je .LBB2_8
; SSE-NEXT: .LBB2_7: # %cond.load7
; SSE-NEXT: pextrq $1, %xmm4, %rax
-; SSE-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1,2],mem[0]
+; SSE-NEXT: insertps $48, (%rax), %xmm3 # xmm3 = xmm3[0,1,2],mem[0]
; SSE-NEXT: movaps %xmm3, %xmm0
; SSE-NEXT: retq
;
@@ -375,14 +375,14 @@ define <4 x float> @gather_v4f32_v4i64_v4i32(float* %base, <4 x i64> %idx, <4 x
; AVX1-NEXT: je .LBB2_2
; AVX1-NEXT: # %bb.1: # %cond.load
; AVX1-NEXT: vmovq %xmm0, %rcx
-; AVX1-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; AVX1-NEXT: vmovss (%rcx), %xmm1 # xmm1 = mem[0],zero,zero,zero
; AVX1-NEXT: vblendps {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; AVX1-NEXT: .LBB2_2: # %else
; AVX1-NEXT: testb $2, %al
; AVX1-NEXT: je .LBB2_4
; AVX1-NEXT: # %bb.3: # %cond.load1
; AVX1-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3]
+; AVX1-NEXT: vinsertps $16, (%rcx), %xmm2, %xmm2 # xmm2 = xmm2[0],mem[0],xmm2[2,3]
; AVX1-NEXT: .LBB2_4: # %else2
; AVX1-NEXT: testb $4, %al
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
@@ -396,12 +396,12 @@ define <4 x float> @gather_v4f32_v4i64_v4i32(float* %base, <4 x i64> %idx, <4 x
; AVX1-NEXT: retq
; AVX1-NEXT: .LBB2_5: # %cond.load4
; AVX1-NEXT: vmovq %xmm0, %rcx
-; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3]
+; AVX1-NEXT: vinsertps $32, (%rcx), %xmm2, %xmm2 # xmm2 = xmm2[0,1],mem[0],xmm2[3]
; AVX1-NEXT: testb $8, %al
; AVX1-NEXT: je .LBB2_8
; AVX1-NEXT: .LBB2_7: # %cond.load7
; AVX1-NEXT: vpextrq $1, %xmm0, %rax
-; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0]
+; AVX1-NEXT: vinsertps $48, (%rax), %xmm2, %xmm2 # xmm2 = xmm2[0,1,2],mem[0]
; AVX1-NEXT: vmovaps %xmm2, %xmm0
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
@@ -419,14 +419,14 @@ define <4 x float> @gather_v4f32_v4i64_v4i32(float* %base, <4 x i64> %idx, <4 x
; AVX2-NEXT: je .LBB2_2
; AVX2-NEXT: # %bb.1: # %cond.load
; AVX2-NEXT: vmovq %xmm0, %rcx
-; AVX2-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; AVX2-NEXT: vmovss (%rcx), %xmm1 # xmm1 = mem[0],zero,zero,zero
; AVX2-NEXT: vblendps {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; AVX2-NEXT: .LBB2_2: # %else
; AVX2-NEXT: testb $2, %al
; AVX2-NEXT: je .LBB2_4
; AVX2-NEXT: # %bb.3: # %cond.load1
; AVX2-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3]
+; AVX2-NEXT: vinsertps $16, (%rcx), %xmm2, %xmm2 # xmm2 = xmm2[0],mem[0],xmm2[2,3]
; AVX2-NEXT: .LBB2_4: # %else2
; AVX2-NEXT: testb $4, %al
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
@@ -440,12 +440,12 @@ define <4 x float> @gather_v4f32_v4i64_v4i32(float* %base, <4 x i64> %idx, <4 x
; AVX2-NEXT: retq
; AVX2-NEXT: .LBB2_5: # %cond.load4
; AVX2-NEXT: vmovq %xmm0, %rcx
-; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3]
+; AVX2-NEXT: vinsertps $32, (%rcx), %xmm2, %xmm2 # xmm2 = xmm2[0,1],mem[0],xmm2[3]
; AVX2-NEXT: testb $8, %al
; AVX2-NEXT: je .LBB2_8
; AVX2-NEXT: .LBB2_7: # %cond.load7
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
-; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0]
+; AVX2-NEXT: vinsertps $48, (%rax), %xmm2, %xmm2 # xmm2 = xmm2[0,1,2],mem[0]
; AVX2-NEXT: vmovaps %xmm2, %xmm0
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
@@ -1040,7 +1040,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; SSE-NEXT: je .LBB4_1
; SSE-NEXT: # %bb.2: # %cond.load
; SSE-NEXT: movq %xmm5, %rcx
-; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE-NEXT: movd (%rcx), %xmm0 # xmm0 = mem[0],zero,zero,zero
; SSE-NEXT: testb $2, %al
; SSE-NEXT: jne .LBB4_4
; SSE-NEXT: jmp .LBB4_5
@@ -1105,7 +1105,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; SSE-NEXT: je .LBB4_19
; SSE-NEXT: # %bb.20: # %cond.load23
; SSE-NEXT: movq %xmm4, %rcx
-; SSE-NEXT: movd {{.*#+}} xmm5 = mem[0],zero,zero,zero
+; SSE-NEXT: movd (%rcx), %xmm5 # xmm5 = mem[0],zero,zero,zero
; SSE-NEXT: testb $2, %al
; SSE-NEXT: jne .LBB4_22
; SSE-NEXT: jmp .LBB4_23
@@ -1174,7 +1174,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; SSE-NEXT: je .LBB4_37
; SSE-NEXT: # %bb.38: # %cond.load72
; SSE-NEXT: movq %xmm4, %rcx
-; SSE-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; SSE-NEXT: movd (%rcx), %xmm2 # xmm2 = mem[0],zero,zero,zero
; SSE-NEXT: testb $2, %al
; SSE-NEXT: jne .LBB4_40
; SSE-NEXT: jmp .LBB4_41
@@ -1260,7 +1260,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; AVX1-NEXT: je .LBB4_2
; AVX1-NEXT: # %bb.1: # %cond.load
; AVX1-NEXT: vmovq %xmm4, %rcx
-; AVX1-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; AVX1-NEXT: vmovd (%rcx), %xmm1 # xmm1 = mem[0],zero,zero,zero
; AVX1-NEXT: .LBB4_2: # %else
; AVX1-NEXT: testb $2, %al
; AVX1-NEXT: je .LBB4_4
@@ -1314,7 +1314,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; AVX1-NEXT: je .LBB4_18
; AVX1-NEXT: # %bb.17: # %cond.load23
; AVX1-NEXT: vmovq %xmm7, %rcx
-; AVX1-NEXT: vmovd {{.*#+}} xmm4 = mem[0],zero,zero,zero
+; AVX1-NEXT: vmovd (%rcx), %xmm4 # xmm4 = mem[0],zero,zero,zero
; AVX1-NEXT: .LBB4_18: # %else27
; AVX1-NEXT: testb $2, %al
; AVX1-NEXT: je .LBB4_20
@@ -1385,7 +1385,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; AVX1-NEXT: je .LBB4_34
; AVX1-NEXT: # %bb.33: # %cond.load72
; AVX1-NEXT: vmovq %xmm7, %rcx
-; AVX1-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; AVX1-NEXT: vmovd (%rcx), %xmm0 # xmm0 = mem[0],zero,zero,zero
; AVX1-NEXT: .LBB4_34: # %else76
; AVX1-NEXT: testb $2, %al
; AVX1-NEXT: je .LBB4_36
@@ -1498,7 +1498,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; AVX2-NEXT: je .LBB4_2
; AVX2-NEXT: # %bb.1: # %cond.load
; AVX2-NEXT: vmovq %xmm3, %rcx
-; AVX2-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; AVX2-NEXT: vmovd (%rcx), %xmm1 # xmm1 = mem[0],zero,zero,zero
; AVX2-NEXT: .LBB4_2: # %else
; AVX2-NEXT: testb $2, %al
; AVX2-NEXT: je .LBB4_4
@@ -1541,7 +1541,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; AVX2-NEXT: je .LBB4_18
; AVX2-NEXT: # %bb.17: # %cond.load23
; AVX2-NEXT: vmovq %xmm3, %rcx
-; AVX2-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; AVX2-NEXT: vmovd (%rcx), %xmm2 # xmm2 = mem[0],zero,zero,zero
; AVX2-NEXT: .LBB4_18: # %else27
; AVX2-NEXT: testb $2, %al
; AVX2-NEXT: je .LBB4_20
@@ -1685,7 +1685,7 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) {
; AVX2-NEXT: jmp .LBB4_32
; AVX2-NEXT: .LBB4_33: # %cond.load72
; AVX2-NEXT: vmovq %xmm3, %rcx
-; AVX2-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; AVX2-NEXT: vmovd (%rcx), %xmm0 # xmm0 = mem[0],zero,zero,zero
; AVX2-NEXT: testb $2, %al
; AVX2-NEXT: je .LBB4_36
; AVX2-NEXT: .LBB4_35: # %cond.load78
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