[PATCH] D74858: [AArch64][SVE] Add intrinsics for non-temporal gather-loads/scatter-stores
Andrzej Warzynski via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 20 05:10:40 PST 2020
andwar added a comment.
Hi @efriedma , thank you for taking a look!
In D74858#1883644 <https://reviews.llvm.org/D74858#1883644>, @efriedma wrote:
> > Note that for the non-temporal gather-loads and scatter-stores "vector base, scalar offset" is the only available addressing mode.
>
> Not sure what you mean by this. The ACLE provides both "vector base, scalar offset" and "scalar base, vector offset"; we should provide corresponding intrinsics, I think.
I'm not being very clear there, sorry. I'm only referring to the LLVM IR intrinsics, which we want to map 1:1 to the actual instructions (and, AFAIK, "scalar base, vector offset" is the only option there).
ACLE indeed defines more addressing modes for non-temporal gather loads and that will require some extra logic. Clang seems like a more natural place to handle that.
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https://reviews.llvm.org/D74858/new/
https://reviews.llvm.org/D74858
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