[PATCH] D74858: [AArch64][SVE] Add intrinsics for non-temporal gather-loads/scatter-stores

[Andrzej Warzynski via Phabricator via llvm-commits]

andwar created this revision.
andwar added reviewers: sdesmalen, efriedma.
Herald added subscribers: llvm-commits, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a project: LLVM.

This patch adds an LLVM IR intrinsics for SVE non-temporal gather loads
and scatter stores:

- @llvm.aarch64.sve.ldnt1.gather
- @llvm.aarch64.sve.stnt1.scatter

These intrinsic map 1-1 to the corresponding SVE instructions (example
for half-words, zero-extending):

- ldnt1h { z0.s }, p0/z, [z0.s, x0]
- stnt1h { z0.s }, p0/z, [z0.s, x0]

Note that for the non-temporal gather-loads and scatter-stores "vector
base, scalar offset" is the only available addressing mode. In terms of
regular gather-loads/scatter-stores, this addressing mode is implemented
with

- llvm.aarch64.sve.ld1.gather.scalar.offset,
- llvm.aarch64.sve.st1.scatter.scalar.offset.

The sve2_mem_gldnt_vs multiclass (and it's counterpart for scatter
stores) from SVEInstrFormats.td was split into:

- sve2_mem_gldnt_32b_ptrs (32bit wide base addresses)
- sve2_mem_gldnt_62b_ptrs (64bit wide base addresses)

This is consistent to what we have for @llvm.aarch64.sve.ld1.scalar.offset.

`performLD1GatherCombine` and `performST1ScatterCombine` from
AArch64ISelLowering.cpp are renamed as `performGatherLoadCombine` and
`performScatterStoreCombine` and used for lowering the new intrinsics.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D74858

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve2-intrinsics-nt-gather-loads.ll
  llvm/test/CodeGen/AArch64/sve2-intrinsics-nt-scatter-stores.ll

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