[llvm] 7a55427 - [SystemZ] Regenerate risbg tests. NFCI.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 19 08:39:42 PST 2020
Author: Simon Pilgrim
Date: 2020-02-19T16:39:28Z
New Revision: 7a554270c030ed8b7074ebd9a339a633b8f45059
URL: https://github.com/llvm/llvm-project/commit/7a554270c030ed8b7074ebd9a339a633b8f45059
DIFF: https://github.com/llvm/llvm-project/commit/7a554270c030ed8b7074ebd9a339a633b8f45059.diff
LOG: [SystemZ] Regenerate risbg tests. NFCI.
Pre-commit for some upcoming SimplifyDemandedBits bitrotate handling.
Added:
Modified:
llvm/test/CodeGen/SystemZ/risbg-01.ll
llvm/test/CodeGen/SystemZ/risbg-02.ll
llvm/test/CodeGen/SystemZ/risbg-03.ll
llvm/test/CodeGen/SystemZ/risbg-04.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/SystemZ/risbg-01.ll b/llvm/test/CodeGen/SystemZ/risbg-01.ll
index 9d86893a403c..28e871c3f724 100644
--- a/llvm/test/CodeGen/SystemZ/risbg-01.ll
+++ b/llvm/test/CodeGen/SystemZ/risbg-01.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test sequences that can use RISBG with a zeroed first operand.
; The tests here assume that RISBLG isn't available.
;
@@ -6,8 +7,11 @@
; Test an extraction of bit 0 from a right-shifted value.
define i32 @f1(i32 %foo) {
; CHECK-LABEL: f1:
-; CHECK: risbg %r2, %r2, 63, 191, 54
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT: risbg %r2, %r2, 63, 191, 54
+; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d
+; CHECK-NEXT: br %r14
%shr = lshr i32 %foo, 10
%and = and i32 %shr, 1
ret i32 %and
@@ -16,8 +20,9 @@ define i32 @f1(i32 %foo) {
; ...and again with i64.
define i64 @f2(i64 %foo) {
; CHECK-LABEL: f2:
-; CHECK: risbg %r2, %r2, 63, 191, 54
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 63, 191, 54
+; CHECK-NEXT: br %r14
%shr = lshr i64 %foo, 10
%and = and i64 %shr, 1
ret i64 %and
@@ -26,8 +31,11 @@ define i64 @f2(i64 %foo) {
; Test an extraction of other bits from a right-shifted value.
define i32 @f3(i32 %foo) {
; CHECK-LABEL: f3:
-; CHECK: risbg %r2, %r2, 60, 189, 42
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT: risbg %r2, %r2, 60, 189, 42
+; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d
+; CHECK-NEXT: br %r14
%shr = lshr i32 %foo, 22
%and = and i32 %shr, 12
ret i32 %and
@@ -36,8 +44,9 @@ define i32 @f3(i32 %foo) {
; ...and again with i64.
define i64 @f4(i64 %foo) {
; CHECK-LABEL: f4:
-; CHECK: risbg %r2, %r2, 60, 189, 42
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 60, 189, 42
+; CHECK-NEXT: br %r14
%shr = lshr i64 %foo, 22
%and = and i64 %shr, 12
ret i64 %and
@@ -47,8 +56,11 @@ define i64 @f4(i64 %foo) {
; The range should be reduced to exclude the zeroed high bits.
define i32 @f5(i32 %foo) {
; CHECK-LABEL: f5:
-; CHECK: risbg %r2, %r2, 34, 188, 62
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT: risbg %r2, %r2, 34, 188, 62
+; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d
+; CHECK-NEXT: br %r14
%shr = lshr i32 %foo, 2
%and = and i32 %shr, -8
ret i32 %and
@@ -57,8 +69,9 @@ define i32 @f5(i32 %foo) {
; ...and again with i64.
define i64 @f6(i64 %foo) {
; CHECK-LABEL: f6:
-; CHECK: risbg %r2, %r2, 2, 188, 62
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 2, 188, 62
+; CHECK-NEXT: br %r14
%shr = lshr i64 %foo, 2
%and = and i64 %shr, -8
ret i64 %and
@@ -68,9 +81,10 @@ define i64 @f6(i64 %foo) {
; and mask.
define i32 @f7(i32 %foo) {
; CHECK-LABEL: f7:
-; CHECK: srl %r2, 2
-; CHECK: nill %r2, 65529
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srl %r2, 2
+; CHECK-NEXT: nill %r2, 65529
+; CHECK-NEXT: br %r14
%shr = lshr i32 %foo, 2
%and = and i32 %shr, -7
ret i32 %and
@@ -79,9 +93,10 @@ define i32 @f7(i32 %foo) {
; ...and again with i64.
define i64 @f8(i64 %foo) {
; CHECK-LABEL: f8:
-; CHECK: srlg %r2, %r2, 2
-; CHECK: nill %r2, 65529
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srlg %r2, %r2, 2
+; CHECK-NEXT: nill %r2, 65529
+; CHECK-NEXT: br %r14
%shr = lshr i64 %foo, 2
%and = and i64 %shr, -7
ret i64 %and
@@ -91,8 +106,11 @@ define i64 @f8(i64 %foo) {
; be reduced to exclude the zeroed low bits.
define i32 @f9(i32 %foo) {
; CHECK-LABEL: f9:
-; CHECK: risbg %r2, %r2, 56, 189, 2
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT: risbg %r2, %r2, 56, 189, 2
+; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d
+; CHECK-NEXT: br %r14
%shr = shl i32 %foo, 2
%and = and i32 %shr, 255
ret i32 %and
@@ -101,8 +119,9 @@ define i32 @f9(i32 %foo) {
; ...and again with i64.
define i64 @f10(i64 %foo) {
; CHECK-LABEL: f10:
-; CHECK: risbg %r2, %r2, 56, 189, 2
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 56, 189, 2
+; CHECK-NEXT: br %r14
%shr = shl i64 %foo, 2
%and = and i64 %shr, 255
ret i64 %and
@@ -112,9 +131,10 @@ define i64 @f10(i64 %foo) {
; and mask.
define i32 @f11(i32 %foo) {
; CHECK-LABEL: f11:
-; CHECK: sll %r2, 2
-; CHECK: nill %r2, 65295
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sll %r2, 2
+; CHECK-NEXT: nill %r2, 65295
+; CHECK-NEXT: br %r14
%shr = shl i32 %foo, 2
%and = and i32 %shr, -241
ret i32 %and
@@ -123,9 +143,10 @@ define i32 @f11(i32 %foo) {
; ...and again with i64.
define i64 @f12(i64 %foo) {
; CHECK-LABEL: f12:
-; CHECK: sllg %r2, %r2, 2
-; CHECK: nill %r2, 65295
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sllg %r2, %r2, 2
+; CHECK-NEXT: nill %r2, 65295
+; CHECK-NEXT: br %r14
%shr = shl i64 %foo, 2
%and = and i64 %shr, -241
ret i64 %and
@@ -136,8 +157,11 @@ define i64 @f12(i64 %foo) {
; shl are not used.
define i32 @f13(i32 %foo) {
; CHECK-LABEL: f13:
-; CHECK: risbg %r2, %r2, 56, 188, 46
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT: risbg %r2, %r2, 56, 188, 46
+; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d
+; CHECK-NEXT: br %r14
%parta = shl i32 %foo, 14
%partb = lshr i32 %foo, 18
%rotl = or i32 %parta, %partb
@@ -148,8 +172,9 @@ define i32 @f13(i32 %foo) {
; ...and again with i64.
define i64 @f14(i64 %foo) {
; CHECK-LABEL: f14:
-; CHECK: risbg %r2, %r2, 56, 188, 14
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 56, 188, 14
+; CHECK-NEXT: br %r14
%parta = shl i64 %foo, 14
%partb = lshr i64 %foo, 50
%rotl = or i64 %parta, %partb
@@ -160,8 +185,11 @@ define i64 @f14(i64 %foo) {
; Try a case in which only the bits from the shl are used.
define i32 @f15(i32 %foo) {
; CHECK-LABEL: f15:
-; CHECK: risbg %r2, %r2, 47, 177, 14
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT: risbg %r2, %r2, 47, 177, 14
+; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d
+; CHECK-NEXT: br %r14
%parta = shl i32 %foo, 14
%partb = lshr i32 %foo, 18
%rotl = or i32 %parta, %partb
@@ -172,8 +200,9 @@ define i32 @f15(i32 %foo) {
; ...and again with i64.
define i64 @f16(i64 %foo) {
; CHECK-LABEL: f16:
-; CHECK: risbg %r2, %r2, 47, 177, 14
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 47, 177, 14
+; CHECK-NEXT: br %r14
%parta = shl i64 %foo, 14
%partb = lshr i64 %foo, 50
%rotl = or i64 %parta, %partb
@@ -185,9 +214,10 @@ define i64 @f16(i64 %foo) {
; This needs a separate shift and mask.
define i32 @f17(i32 %foo) {
; CHECK-LABEL: f17:
-; CHECK: rll %r2, %r2, 4
-; CHECK: nilf %r2, 126
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: rll %r2, %r2, 4
+; CHECK-NEXT: nilf %r2, 126
+; CHECK-NEXT: br %r14
%parta = shl i32 %foo, 4
%partb = lshr i32 %foo, 28
%rotl = or i32 %parta, %partb
@@ -198,8 +228,9 @@ define i32 @f17(i32 %foo) {
; ...and for i64, where RISBG should do the rotate too.
define i64 @f18(i64 %foo) {
; CHECK-LABEL: f18:
-; CHECK: risbg %r2, %r2, 57, 190, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 57, 190, 4
+; CHECK-NEXT: br %r14
%parta = shl i64 %foo, 4
%partb = lshr i64 %foo, 60
%rotl = or i64 %parta, %partb
@@ -211,9 +242,10 @@ define i64 @f18(i64 %foo) {
; This needs a separate shift and mask.
define i32 @f19(i32 %foo) {
; CHECK-LABEL: f19:
-; CHECK: sra %r2, 28
-; CHECK: nilf %r2, 30
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sra %r2, 28
+; CHECK-NEXT: nilf %r2, 30
+; CHECK-NEXT: br %r14
%shr = ashr i32 %foo, 28
%and = and i32 %shr, 30
ret i32 %and
@@ -222,9 +254,10 @@ define i32 @f19(i32 %foo) {
; ...and again with i64. In this case RISBG is the best way of doing the AND.
define i64 @f20(i64 %foo) {
; CHECK-LABEL: f20:
-; CHECK: srag [[REG:%r[0-5]]], %r2, 60
-; CHECK: risbg %r2, [[REG]], 59, 190, 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srag %r0, %r2, 60
+; CHECK-NEXT: risbg %r2, %r0, 59, 190, 0
+; CHECK-NEXT: br %r14
%shr = ashr i64 %foo, 60
%and = and i64 %shr, 30
ret i64 %and
@@ -236,9 +269,14 @@ define i64 @f20(i64 %foo) {
; NOTE: the extra move to %r2 should not be needed (temporary FAIL)
define i32 @f21(i32 %foo, i32 *%dest) {
; CHECK-LABEL: f21:
-; CHECK: risbg %r0, %r2, 60, 190, 36
-; CHECK: lr %r2, %r0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT: risbg %r0, %r2, 60, 190, 36
+; CHECK-NEXT: lr %r1, %r2
+; CHECK-NEXT: sra %r1, 28
+; CHECK-NEXT: st %r1, 0(%r3)
+; CHECK-NEXT: lr %r2, %r0
+; CHECK-NEXT: br %r14
%shr = ashr i32 %foo, 28
store i32 %shr, i32 *%dest
%and = and i32 %shr, 14
@@ -248,8 +286,11 @@ define i32 @f21(i32 %foo, i32 *%dest) {
; ...and again with i64.
define i64 @f22(i64 %foo, i64 *%dest) {
; CHECK-LABEL: f22:
-; CHECK: risbg %r2, %r2, 60, 190, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srag %r0, %r2, 60
+; CHECK-NEXT: risbg %r2, %r2, 60, 190, 4
+; CHECK-NEXT: stg %r0, 0(%r3)
+; CHECK-NEXT: br %r14
%shr = ashr i64 %foo, 60
store i64 %shr, i64 *%dest
%and = and i64 %shr, 14
@@ -260,8 +301,9 @@ define i64 @f22(i64 %foo, i64 *%dest) {
; natural zero extension.
define i64 @f23(i64 %foo) {
; CHECK-LABEL: f23:
-; CHECK: risbg %r2, %r2, 56, 191, 62
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 56, 191, 62
+; CHECK-NEXT: br %r14
%shr = lshr i64 %foo, 2
%and = and i64 %shr, 255
ret i64 %and
@@ -271,9 +313,10 @@ define i64 @f23(i64 %foo) {
; mask and rotate.
define i32 @f24(i32 %foo) {
; CHECK-LABEL: f24:
-; CHECK: nilf %r2, 254
-; CHECK: rll %r2, %r2, 29
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: nilf %r2, 254
+; CHECK-NEXT: rll %r2, %r2, 29
+; CHECK-NEXT: br %r14
%and = and i32 %foo, 254
%parta = lshr i32 %and, 3
%partb = shl i32 %and, 29
@@ -284,8 +327,9 @@ define i32 @f24(i32 %foo) {
; ...and again with i64, where a single RISBG is enough.
define i64 @f25(i64 %foo) {
; CHECK-LABEL: f25:
-; CHECK: risbg %r2, %r2, 57, 187, 3
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 57, 187, 3
+; CHECK-NEXT: br %r14
%and = and i64 %foo, 14
%parta = shl i64 %and, 3
%partb = lshr i64 %and, 61
@@ -297,8 +341,10 @@ define i64 @f25(i64 %foo) {
; This again needs a separate mask and rotate.
define i32 @f26(i32 %foo) {
; CHECK-LABEL: f26:
-; CHECK: rll %r2, %r2, 5
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: nill %r2, 65487
+; CHECK-NEXT: rll %r2, %r2, 5
+; CHECK-NEXT: br %r14
%and = and i32 %foo, -49
%parta = shl i32 %and, 5
%partb = lshr i32 %and, 27
@@ -309,8 +355,9 @@ define i32 @f26(i32 %foo) {
; ...and again with i64, where a single RISBG is OK.
define i64 @f27(i64 %foo) {
; CHECK-LABEL: f27:
-; CHECK: risbg %r2, %r2, 55, 180, 5
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 55, 180, 5
+; CHECK-NEXT: br %r14
%and = and i64 %foo, -49
%parta = shl i64 %and, 5
%partb = lshr i64 %and, 59
@@ -321,8 +368,11 @@ define i64 @f27(i64 %foo) {
; Test a case where the AND comes before a shift left.
define i32 @f28(i32 %foo) {
; CHECK-LABEL: f28:
-; CHECK: risbg %r2, %r2, 32, 173, 17
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT: risbg %r2, %r2, 32, 173, 17
+; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d
+; CHECK-NEXT: br %r14
%and = and i32 %foo, 32766
%shl = shl i32 %and, 17
ret i32 %shl
@@ -331,8 +381,9 @@ define i32 @f28(i32 %foo) {
; ...and again with i64.
define i64 @f29(i64 %foo) {
; CHECK-LABEL: f29:
-; CHECK: risbg %r2, %r2, 0, 141, 49
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 0, 141, 49
+; CHECK-NEXT: br %r14
%and = and i64 %foo, 32766
%shl = shl i64 %and, 49
ret i64 %shl
@@ -341,8 +392,11 @@ define i64 @f29(i64 %foo) {
; Test the next shift up from f28, in which the mask should get shortened.
define i32 @f30(i32 %foo) {
; CHECK-LABEL: f30:
-; CHECK: risbg %r2, %r2, 32, 172, 18
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT: risbg %r2, %r2, 32, 172, 18
+; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d
+; CHECK-NEXT: br %r14
%and = and i32 %foo, 32766
%shl = shl i32 %and, 18
ret i32 %shl
@@ -351,8 +405,9 @@ define i32 @f30(i32 %foo) {
; ...and again with i64.
define i64 @f31(i64 %foo) {
; CHECK-LABEL: f31:
-; CHECK: risbg %r2, %r2, 0, 140, 50
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 0, 140, 50
+; CHECK-NEXT: br %r14
%and = and i64 %foo, 32766
%shl = shl i64 %and, 50
ret i64 %shl
@@ -362,8 +417,10 @@ define i64 @f31(i64 %foo) {
; We can't use RISBG for the shift in that case.
define i32 @f32(i32 %foo) {
; CHECK-LABEL: f32:
-; CHECK: sll %r2
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: nilf %r2, 4194297
+; CHECK-NEXT: sll %r2, 10
+; CHECK-NEXT: br %r14
%and = and i32 %foo, -7
%shl = shl i32 %and, 10
ret i32 %shl
@@ -372,8 +429,12 @@ define i32 @f32(i32 %foo) {
; ...and again with i64.
define i64 @f33(i64 %foo) {
; CHECK-LABEL: f33:
-; CHECK: sllg %r2
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: llihf %r0, 4194303
+; CHECK-NEXT: oilf %r0, 4294967289
+; CHECK-NEXT: ngr %r0, %r2
+; CHECK-NEXT: sllg %r2, %r0, 10
+; CHECK-NEXT: br %r14
%and = and i64 %foo, -7
%shl = shl i64 %and, 10
ret i64 %shl
@@ -382,8 +443,11 @@ define i64 @f33(i64 %foo) {
; Test a case where the AND comes before a shift right.
define i32 @f34(i32 %foo) {
; CHECK-LABEL: f34:
-; CHECK: risbg %r2, %r2, 57, 191, 55
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT: risbg %r2, %r2, 57, 191, 55
+; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d
+; CHECK-NEXT: br %r14
%and = and i32 %foo, 65535
%shl = lshr i32 %and, 9
ret i32 %shl
@@ -392,8 +456,9 @@ define i32 @f34(i32 %foo) {
; ...and again with i64.
define i64 @f35(i64 %foo) {
; CHECK-LABEL: f35:
-; CHECK: risbg %r2, %r2, 57, 191, 55
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 57, 191, 55
+; CHECK-NEXT: br %r14
%and = and i64 %foo, 65535
%shl = lshr i64 %and, 9
ret i64 %shl
@@ -403,8 +468,10 @@ define i64 @f35(i64 %foo) {
; We can't use RISBG for the shift in that case.
define i32 @f36(i32 %foo) {
; CHECK-LABEL: f36:
-; CHECK: srl %r2
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: nill %r2, 65510
+; CHECK-NEXT: srl %r2, 1
+; CHECK-NEXT: br %r14
%and = and i32 %foo, -25
%shl = lshr i32 %and, 1
ret i32 %shl
@@ -413,8 +480,10 @@ define i32 @f36(i32 %foo) {
; ...and again with i64.
define i64 @f37(i64 %foo) {
; CHECK-LABEL: f37:
-; CHECK: srlg %r2
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: nill %r2, 65510
+; CHECK-NEXT: srlg %r2, %r2, 1
+; CHECK-NEXT: br %r14
%and = and i64 %foo, -25
%shl = lshr i64 %and, 1
ret i64 %shl
@@ -424,9 +493,10 @@ define i64 @f37(i64 %foo) {
; use RISBG there.
define i64 @f38(i64 %foo) {
; CHECK-LABEL: f38:
-; CHECK: srag {{%r[0-5]}}
-; CHECK: sllg {{%r[0-5]}}
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srag %r0, %r2, 32
+; CHECK-NEXT: sllg %r2, %r0, 5
+; CHECK-NEXT: br %r14
%ashr = ashr i64 %foo, 32
%shl = shl i64 %ashr, 5
ret i64 %shl
@@ -435,9 +505,11 @@ define i64 @f38(i64 %foo) {
; Try a similar thing in which no shifted sign bits are kept.
define i64 @f39(i64 %foo, i64 *%dest) {
; CHECK-LABEL: f39:
-; CHECK: srag [[REG:%r[01345]]], %r2, 35
-; CHECK: risbg %r2, %r2, 33, 189, 31
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srag %r0, %r2, 35
+; CHECK-NEXT: risbg %r2, %r2, 33, 189, 31
+; CHECK-NEXT: stg %r0, 0(%r3)
+; CHECK-NEXT: br %r14
%ashr = ashr i64 %foo, 35
store i64 %ashr, i64 *%dest
%shl = shl i64 %ashr, 2
@@ -448,9 +520,11 @@ define i64 @f39(i64 %foo, i64 *%dest) {
; ...and again with the next highest shift value, where one sign bit is kept.
define i64 @f40(i64 %foo, i64 *%dest) {
; CHECK-LABEL: f40:
-; CHECK: srag [[REG:%r[01345]]], %r2, 36
-; CHECK: risbg %r2, [[REG]], 33, 189, 2
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srag %r0, %r2, 36
+; CHECK-NEXT: risbg %r2, %r0, 33, 189, 2
+; CHECK-NEXT: stg %r0, 0(%r3)
+; CHECK-NEXT: br %r14
%ashr = ashr i64 %foo, 36
store i64 %ashr, i64 *%dest
%shl = shl i64 %ashr, 2
@@ -460,9 +534,11 @@ define i64 @f40(i64 %foo, i64 *%dest) {
; Check a case where the result is zero-extended.
define i64 @f41(i32 %a) {
-; CHECK-LABEL: f41
-; CHECK: risbg %r2, %r2, 36, 191, 62
-; CHECK: br %r14
+; CHECK-LABEL: f41:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT: risbg %r2, %r2, 36, 191, 62
+; CHECK-NEXT: br %r14
%shl = shl i32 %a, 2
%shr = lshr i32 %shl, 4
%ext = zext i32 %shr to i64
@@ -474,10 +550,11 @@ define i64 @f41(i32 %a) {
; when testing whether the shifted-in bits of the shift right were significant.
define i64 @f42(i1 %x) {
; CHECK-LABEL: f42:
-; CHECK: nilf %r2, 1
-; CHECK: lcr %r0, %r2
-; CHECK: llgcr %r2, %r0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: nilf %r2, 1
+; CHECK-NEXT: lcr %r0, %r2
+; CHECK-NEXT: llgcr %r2, %r0
+; CHECK-NEXT: br %r14
%ext = sext i1 %x to i8
%ext2 = zext i8 %ext to i64
ret i64 %ext2
@@ -486,8 +563,10 @@ define i64 @f42(i1 %x) {
; Check that we get the case where a 64-bit shift is used by a 32-bit and.
define signext i32 @f43(i64 %x) {
; CHECK-LABEL: f43:
-; CHECK: risbg [[REG:%r[0-5]]], %r2, 32, 189, 52
-; CHECK: lgfr %r2, [[REG]]
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r0, %r2, 32, 189, 52
+; CHECK-NEXT: lgfr %r2, %r0
+; CHECK-NEXT: br %r14
%shr3 = lshr i64 %x, 12
%shr3.tr = trunc i64 %shr3 to i32
%conv = and i32 %shr3.tr, -4
@@ -497,7 +576,11 @@ define signext i32 @f43(i64 %x) {
; Check that we don't get the case where the 32-bit and mask is not contiguous
define signext i32 @f44(i64 %x) {
; CHECK-LABEL: f44:
-; CHECK: srlg [[REG:%r[0-5]]], %r2, 12
+; CHECK: # %bb.0:
+; CHECK-NEXT: srlg %r0, %r2, 12
+; CHECK-NEXT: lghi %r2, 10
+; CHECK-NEXT: ngr %r2, %r0
+; CHECK-NEXT: br %r14
%shr4 = lshr i64 %x, 12
%conv = trunc i64 %shr4 to i32
%and = and i32 %conv, 10
diff --git a/llvm/test/CodeGen/SystemZ/risbg-02.ll b/llvm/test/CodeGen/SystemZ/risbg-02.ll
index 094005acae4b..a6947dcefcbb 100644
--- a/llvm/test/CodeGen/SystemZ/risbg-02.ll
+++ b/llvm/test/CodeGen/SystemZ/risbg-02.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test sequences that can use RISBG with a normal first operand.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -5,8 +6,12 @@
; Test a case with two ANDs.
define i32 @f1(i32 %a, i32 %b) {
; CHECK-LABEL: f1:
-; CHECK: risbg %r2, %r3, 60, 62, 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d
+; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT: risbg %r2, %r3, 60, 62, 0
+; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d
+; CHECK-NEXT: br %r14
%anda = and i32 %a, -15
%andb = and i32 %b, 14
%or = or i32 %anda, %andb
@@ -16,8 +21,9 @@ define i32 @f1(i32 %a, i32 %b) {
; ...and again with i64.
define i64 @f2(i64 %a, i64 %b) {
; CHECK-LABEL: f2:
-; CHECK: risbg %r2, %r3, 60, 62, 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r3, 60, 62, 0
+; CHECK-NEXT: br %r14
%anda = and i64 %a, -15
%andb = and i64 %b, 14
%or = or i64 %anda, %andb
@@ -27,8 +33,12 @@ define i64 @f2(i64 %a, i64 %b) {
; Test a case with two ANDs and a shift.
define i32 @f3(i32 %a, i32 %b) {
; CHECK-LABEL: f3:
-; CHECK: risbg %r2, %r3, 60, 63, 56
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d
+; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT: risbg %r2, %r3, 60, 63, 56
+; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d
+; CHECK-NEXT: br %r14
%anda = and i32 %a, -16
%shr = lshr i32 %b, 8
%andb = and i32 %shr, 15
@@ -39,8 +49,9 @@ define i32 @f3(i32 %a, i32 %b) {
; ...and again with i64.
define i64 @f4(i64 %a, i64 %b) {
; CHECK-LABEL: f4:
-; CHECK: risbg %r2, %r3, 60, 63, 56
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r3, 60, 63, 56
+; CHECK-NEXT: br %r14
%anda = and i64 %a, -16
%shr = lshr i64 %b, 8
%andb = and i64 %shr, 15
@@ -51,8 +62,12 @@ define i64 @f4(i64 %a, i64 %b) {
; Test a case with a single AND and a left shift.
define i32 @f5(i32 %a, i32 %b) {
; CHECK-LABEL: f5:
-; CHECK: risbg %r2, %r3, 32, 53, 10
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d
+; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT: risbg %r2, %r3, 32, 53, 10
+; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d
+; CHECK-NEXT: br %r14
%anda = and i32 %a, 1023
%shlb = shl i32 %b, 10
%or = or i32 %anda, %shlb
@@ -62,8 +77,9 @@ define i32 @f5(i32 %a, i32 %b) {
; ...and again with i64.
define i64 @f6(i64 %a, i64 %b) {
; CHECK-LABEL: f6:
-; CHECK: risbg %r2, %r3, 0, 53, 10
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r3, 0, 53, 10
+; CHECK-NEXT: br %r14
%anda = and i64 %a, 1023
%shlb = shl i64 %b, 10
%or = or i64 %anda, %shlb
@@ -73,8 +89,12 @@ define i64 @f6(i64 %a, i64 %b) {
; Test a case with a single AND and a right shift.
define i32 @f7(i32 %a, i32 %b) {
; CHECK-LABEL: f7:
-; CHECK: risbg %r2, %r3, 40, 63, 56
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d
+; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT: risbg %r2, %r3, 40, 63, 56
+; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d
+; CHECK-NEXT: br %r14
%anda = and i32 %a, -16777216
%shrb = lshr i32 %b, 8
%or = or i32 %anda, %shrb
@@ -84,8 +104,9 @@ define i32 @f7(i32 %a, i32 %b) {
; ...and again with i64.
define i64 @f8(i64 %a, i64 %b) {
; CHECK-LABEL: f8:
-; CHECK: risbg %r2, %r3, 8, 63, 56
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r3, 8, 63, 56
+; CHECK-NEXT: br %r14
%anda = and i64 %a, -72057594037927936
%shrb = lshr i64 %b, 8
%or = or i64 %anda, %shrb
@@ -96,8 +117,10 @@ define i64 @f8(i64 %a, i64 %b) {
; ands with complement masks.
define signext i32 @f9(i64 %x, i32 signext %y) {
; CHECK-LABEL: f9:
-; CHECK: risbg [[REG:%r[0-5]]], %r2, 48, 63, 16
-; CHECK: lgfr %r2, [[REG]]
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r3, %r2, 48, 63, 16
+; CHECK-NEXT: lgfr %r2, %r3
+; CHECK-NEXT: br %r14
%shr6 = lshr i64 %x, 48
%conv = trunc i64 %shr6 to i32
%and1 = and i32 %y, -65536
@@ -109,7 +132,11 @@ define signext i32 @f9(i64 %x, i32 signext %y) {
; ands with incompatible masks.
define signext i32 @f10(i64 %x, i32 signext %y) {
; CHECK-LABEL: f10:
-; CHECK: nilf %r3, 4278190080
+; CHECK: # %bb.0:
+; CHECK-NEXT: nilf %r3, 4278190080
+; CHECK-NEXT: rosbg %r3, %r2, 48, 63, 16
+; CHECK-NEXT: lgfr %r2, %r3
+; CHECK-NEXT: br %r14
%shr6 = lshr i64 %x, 48
%conv = trunc i64 %shr6 to i32
%and1 = and i32 %y, -16777216
diff --git a/llvm/test/CodeGen/SystemZ/risbg-03.ll b/llvm/test/CodeGen/SystemZ/risbg-03.ll
index c3c08ad17961..b637f40874b7 100644
--- a/llvm/test/CodeGen/SystemZ/risbg-03.ll
+++ b/llvm/test/CodeGen/SystemZ/risbg-03.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test use of RISBG vs RISBGN on zEC12.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s
@@ -5,8 +6,9 @@
; On zEC12, we generally prefer RISBGN.
define i64 @f1(i64 %a, i64 %b) {
; CHECK-LABEL: f1:
-; CHECK: risbgn %r2, %r3, 60, 62, 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbgn %r2, %r3, 60, 62, 0
+; CHECK-NEXT: br %r14
%anda = and i64 %a, -15
%andb = and i64 %b, 14
%or = or i64 %anda, %andb
@@ -16,9 +18,12 @@ define i64 @f1(i64 %a, i64 %b) {
; But we may fall back to RISBG if we can use the condition code.
define i64 @f2(i64 %a, i64 %b, i32* %c) {
; CHECK-LABEL: f2:
-; CHECK: risbg %r2, %r3, 60, 62, 0
-; CHECK-NEXT: ipm
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r3, 60, 62, 0
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risblg %r0, %r0, 31, 159, 35
+; CHECK-NEXT: st %r0, 0(%r4)
+; CHECK-NEXT: br %r14
%anda = and i64 %a, -15
%andb = and i64 %b, 14
%or = or i64 %anda, %andb
diff --git a/llvm/test/CodeGen/SystemZ/risbg-04.ll b/llvm/test/CodeGen/SystemZ/risbg-04.ll
index 24eb1422d8ba..9b4c076cfb2c 100644
--- a/llvm/test/CodeGen/SystemZ/risbg-04.ll
+++ b/llvm/test/CodeGen/SystemZ/risbg-04.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test sequences that can use RISBG with a zeroed first operand.
; The tests here assume that RISBLG is available.
;
@@ -6,8 +7,9 @@
; Test an extraction of bit 0 from a right-shifted value.
define i32 @f1(i32 %foo) {
; CHECK-LABEL: f1:
-; CHECK: risblg %r2, %r2, 31, 159, 54
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risblg %r2, %r2, 31, 159, 54
+; CHECK-NEXT: br %r14
%shr = lshr i32 %foo, 10
%and = and i32 %shr, 1
ret i32 %and
@@ -16,8 +18,9 @@ define i32 @f1(i32 %foo) {
; ...and again with i64.
define i64 @f2(i64 %foo) {
; CHECK-LABEL: f2:
-; CHECK: risbg %r2, %r2, 63, 191, 54
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 63, 191, 54
+; CHECK-NEXT: br %r14
%shr = lshr i64 %foo, 10
%and = and i64 %shr, 1
ret i64 %and
@@ -26,8 +29,9 @@ define i64 @f2(i64 %foo) {
; Test an extraction of other bits from a right-shifted value.
define i32 @f3(i32 %foo) {
; CHECK-LABEL: f3:
-; CHECK: risblg %r2, %r2, 28, 157, 42
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risblg %r2, %r2, 28, 157, 42
+; CHECK-NEXT: br %r14
%shr = lshr i32 %foo, 22
%and = and i32 %shr, 12
ret i32 %and
@@ -36,8 +40,9 @@ define i32 @f3(i32 %foo) {
; ...and again with i64.
define i64 @f4(i64 %foo) {
; CHECK-LABEL: f4:
-; CHECK: risbg %r2, %r2, 60, 189, 42
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 60, 189, 42
+; CHECK-NEXT: br %r14
%shr = lshr i64 %foo, 22
%and = and i64 %shr, 12
ret i64 %and
@@ -47,8 +52,9 @@ define i64 @f4(i64 %foo) {
; The range should be reduced to exclude the zeroed high bits.
define i32 @f5(i32 %foo) {
; CHECK-LABEL: f5:
-; CHECK: risblg %r2, %r2, 2, 156, 62
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risblg %r2, %r2, 2, 156, 62
+; CHECK-NEXT: br %r14
%shr = lshr i32 %foo, 2
%and = and i32 %shr, -8
ret i32 %and
@@ -57,8 +63,9 @@ define i32 @f5(i32 %foo) {
; ...and again with i64.
define i64 @f6(i64 %foo) {
; CHECK-LABEL: f6:
-; CHECK: risbg %r2, %r2, 2, 188, 62
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 2, 188, 62
+; CHECK-NEXT: br %r14
%shr = lshr i64 %foo, 2
%and = and i64 %shr, -8
ret i64 %and
@@ -68,9 +75,10 @@ define i64 @f6(i64 %foo) {
; and mask.
define i32 @f7(i32 %foo) {
; CHECK-LABEL: f7:
-; CHECK: srl %r2, 2
-; CHECK: nill %r2, 65529
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srl %r2, 2
+; CHECK-NEXT: nill %r2, 65529
+; CHECK-NEXT: br %r14
%shr = lshr i32 %foo, 2
%and = and i32 %shr, -7
ret i32 %and
@@ -79,9 +87,10 @@ define i32 @f7(i32 %foo) {
; ...and again with i64.
define i64 @f8(i64 %foo) {
; CHECK-LABEL: f8:
-; CHECK: srlg %r2, %r2, 2
-; CHECK: nill %r2, 65529
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srlg %r2, %r2, 2
+; CHECK-NEXT: nill %r2, 65529
+; CHECK-NEXT: br %r14
%shr = lshr i64 %foo, 2
%and = and i64 %shr, -7
ret i64 %and
@@ -91,8 +100,9 @@ define i64 @f8(i64 %foo) {
; be reduced to exclude the zeroed low bits.
define i32 @f9(i32 %foo) {
; CHECK-LABEL: f9:
-; CHECK: risblg %r2, %r2, 24, 157, 2
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risblg %r2, %r2, 24, 157, 2
+; CHECK-NEXT: br %r14
%shr = shl i32 %foo, 2
%and = and i32 %shr, 255
ret i32 %and
@@ -101,8 +111,9 @@ define i32 @f9(i32 %foo) {
; ...and again with i64.
define i64 @f10(i64 %foo) {
; CHECK-LABEL: f10:
-; CHECK: risbg %r2, %r2, 56, 189, 2
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 56, 189, 2
+; CHECK-NEXT: br %r14
%shr = shl i64 %foo, 2
%and = and i64 %shr, 255
ret i64 %and
@@ -112,9 +123,10 @@ define i64 @f10(i64 %foo) {
; and mask.
define i32 @f11(i32 %foo) {
; CHECK-LABEL: f11:
-; CHECK: sll %r2, 2
-; CHECK: nill %r2, 65295
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sll %r2, 2
+; CHECK-NEXT: nill %r2, 65295
+; CHECK-NEXT: br %r14
%shr = shl i32 %foo, 2
%and = and i32 %shr, -241
ret i32 %and
@@ -123,9 +135,10 @@ define i32 @f11(i32 %foo) {
; ...and again with i64.
define i64 @f12(i64 %foo) {
; CHECK-LABEL: f12:
-; CHECK: sllg %r2, %r2, 2
-; CHECK: nill %r2, 65295
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sllg %r2, %r2, 2
+; CHECK-NEXT: nill %r2, 65295
+; CHECK-NEXT: br %r14
%shr = shl i64 %foo, 2
%and = and i64 %shr, -241
ret i64 %and
@@ -136,8 +149,9 @@ define i64 @f12(i64 %foo) {
; shl are not used.
define i32 @f13(i32 %foo) {
; CHECK-LABEL: f13:
-; CHECK: risblg %r2, %r2, 24, 156, 46
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risblg %r2, %r2, 24, 156, 46
+; CHECK-NEXT: br %r14
%parta = shl i32 %foo, 14
%partb = lshr i32 %foo, 18
%rotl = or i32 %parta, %partb
@@ -148,8 +162,9 @@ define i32 @f13(i32 %foo) {
; ...and again with i64.
define i64 @f14(i64 %foo) {
; CHECK-LABEL: f14:
-; CHECK: risbg %r2, %r2, 56, 188, 14
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 56, 188, 14
+; CHECK-NEXT: br %r14
%parta = shl i64 %foo, 14
%partb = lshr i64 %foo, 50
%rotl = or i64 %parta, %partb
@@ -160,8 +175,9 @@ define i64 @f14(i64 %foo) {
; Try a case in which only the bits from the shl are used.
define i32 @f15(i32 %foo) {
; CHECK-LABEL: f15:
-; CHECK: risblg %r2, %r2, 15, 145, 14
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risblg %r2, %r2, 15, 145, 14
+; CHECK-NEXT: br %r14
%parta = shl i32 %foo, 14
%partb = lshr i32 %foo, 18
%rotl = or i32 %parta, %partb
@@ -172,8 +188,9 @@ define i32 @f15(i32 %foo) {
; ...and again with i64.
define i64 @f16(i64 %foo) {
; CHECK-LABEL: f16:
-; CHECK: risbg %r2, %r2, 47, 177, 14
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 47, 177, 14
+; CHECK-NEXT: br %r14
%parta = shl i64 %foo, 14
%partb = lshr i64 %foo, 50
%rotl = or i64 %parta, %partb
@@ -185,9 +202,10 @@ define i64 @f16(i64 %foo) {
; This needs a separate shift and mask.
define i32 @f17(i32 %foo) {
; CHECK-LABEL: f17:
-; CHECK: rll %r2, %r2, 4
-; CHECK: nilf %r2, 126
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: rll %r2, %r2, 4
+; CHECK-NEXT: nilf %r2, 126
+; CHECK-NEXT: br %r14
%parta = shl i32 %foo, 4
%partb = lshr i32 %foo, 28
%rotl = or i32 %parta, %partb
@@ -198,8 +216,9 @@ define i32 @f17(i32 %foo) {
; ...and for i64, where RISBG should do the rotate too.
define i64 @f18(i64 %foo) {
; CHECK-LABEL: f18:
-; CHECK: risbg %r2, %r2, 57, 190, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 57, 190, 4
+; CHECK-NEXT: br %r14
%parta = shl i64 %foo, 4
%partb = lshr i64 %foo, 60
%rotl = or i64 %parta, %partb
@@ -211,9 +230,10 @@ define i64 @f18(i64 %foo) {
; This needs a separate shift and mask.
define i32 @f19(i32 %foo) {
; CHECK-LABEL: f19:
-; CHECK: sra %r2, 28
-; CHECK: nilf %r2, 30
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sra %r2, 28
+; CHECK-NEXT: nilf %r2, 30
+; CHECK-NEXT: br %r14
%shr = ashr i32 %foo, 28
%and = and i32 %shr, 30
ret i32 %and
@@ -222,9 +242,10 @@ define i32 @f19(i32 %foo) {
; ...and again with i64. In this case RISBG is the best way of doing the AND.
define i64 @f20(i64 %foo) {
; CHECK-LABEL: f20:
-; CHECK: srag [[REG:%r[0-5]]], %r2, 60
-; CHECK: risbg %r2, [[REG]], 59, 190, 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srag %r0, %r2, 60
+; CHECK-NEXT: risbg %r2, %r0, 59, 190, 0
+; CHECK-NEXT: br %r14
%shr = ashr i64 %foo, 60
%and = and i64 %shr, 30
ret i64 %and
@@ -235,8 +256,11 @@ define i64 @f20(i64 %foo) {
; an lshr.
define i32 @f21(i32 %foo, i32 *%dest) {
; CHECK-LABEL: f21:
-; CHECK: risblg %r2, %r2, 28, 158, 36
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srak %r0, %r2, 28
+; CHECK-NEXT: risblg %r2, %r2, 28, 158, 36
+; CHECK-NEXT: st %r0, 0(%r3)
+; CHECK-NEXT: br %r14
%shr = ashr i32 %foo, 28
store i32 %shr, i32 *%dest
%and = and i32 %shr, 14
@@ -246,8 +270,11 @@ define i32 @f21(i32 %foo, i32 *%dest) {
; ...and again with i64.
define i64 @f22(i64 %foo, i64 *%dest) {
; CHECK-LABEL: f22:
-; CHECK: risbg %r2, %r2, 60, 190, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srag %r0, %r2, 60
+; CHECK-NEXT: risbg %r2, %r2, 60, 190, 4
+; CHECK-NEXT: stg %r0, 0(%r3)
+; CHECK-NEXT: br %r14
%shr = ashr i64 %foo, 60
store i64 %shr, i64 *%dest
%and = and i64 %shr, 14
@@ -258,8 +285,9 @@ define i64 @f22(i64 %foo, i64 *%dest) {
; natural zero extension.
define i64 @f23(i64 %foo) {
; CHECK-LABEL: f23:
-; CHECK: risbg %r2, %r2, 56, 191, 62
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 56, 191, 62
+; CHECK-NEXT: br %r14
%shr = lshr i64 %foo, 2
%and = and i64 %shr, 255
ret i64 %and
@@ -269,9 +297,10 @@ define i64 @f23(i64 %foo) {
; mask and rotate.
define i32 @f24(i32 %foo) {
; CHECK-LABEL: f24:
-; CHECK: nilf %r2, 254
-; CHECK: rll %r2, %r2, 29
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: nilf %r2, 254
+; CHECK-NEXT: rll %r2, %r2, 29
+; CHECK-NEXT: br %r14
%and = and i32 %foo, 254
%parta = lshr i32 %and, 3
%partb = shl i32 %and, 29
@@ -282,8 +311,9 @@ define i32 @f24(i32 %foo) {
; ...and again with i64, where a single RISBG is enough.
define i64 @f25(i64 %foo) {
; CHECK-LABEL: f25:
-; CHECK: risbg %r2, %r2, 57, 187, 3
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 57, 187, 3
+; CHECK-NEXT: br %r14
%and = and i64 %foo, 14
%parta = shl i64 %and, 3
%partb = lshr i64 %and, 61
@@ -295,8 +325,10 @@ define i64 @f25(i64 %foo) {
; This again needs a separate mask and rotate.
define i32 @f26(i32 %foo) {
; CHECK-LABEL: f26:
-; CHECK: rll %r2, %r2, 5
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: nill %r2, 65487
+; CHECK-NEXT: rll %r2, %r2, 5
+; CHECK-NEXT: br %r14
%and = and i32 %foo, -49
%parta = shl i32 %and, 5
%partb = lshr i32 %and, 27
@@ -307,8 +339,9 @@ define i32 @f26(i32 %foo) {
; ...and again with i64, where a single RISBG is OK.
define i64 @f27(i64 %foo) {
; CHECK-LABEL: f27:
-; CHECK: risbg %r2, %r2, 55, 180, 5
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 55, 180, 5
+; CHECK-NEXT: br %r14
%and = and i64 %foo, -49
%parta = shl i64 %and, 5
%partb = lshr i64 %and, 59
@@ -319,8 +352,9 @@ define i64 @f27(i64 %foo) {
; Test a case where the AND comes before a shift left.
define i32 @f28(i32 %foo) {
; CHECK-LABEL: f28:
-; CHECK: risblg %r2, %r2, 0, 141, 17
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risblg %r2, %r2, 0, 141, 17
+; CHECK-NEXT: br %r14
%and = and i32 %foo, 32766
%shl = shl i32 %and, 17
ret i32 %shl
@@ -329,8 +363,9 @@ define i32 @f28(i32 %foo) {
; ...and again with i64.
define i64 @f29(i64 %foo) {
; CHECK-LABEL: f29:
-; CHECK: risbg %r2, %r2, 0, 141, 49
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 0, 141, 49
+; CHECK-NEXT: br %r14
%and = and i64 %foo, 32766
%shl = shl i64 %and, 49
ret i64 %shl
@@ -339,8 +374,9 @@ define i64 @f29(i64 %foo) {
; Test the next shift up from f28, in which the mask should get shortened.
define i32 @f30(i32 %foo) {
; CHECK-LABEL: f30:
-; CHECK: risblg %r2, %r2, 0, 140, 18
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risblg %r2, %r2, 0, 140, 18
+; CHECK-NEXT: br %r14
%and = and i32 %foo, 32766
%shl = shl i32 %and, 18
ret i32 %shl
@@ -349,8 +385,9 @@ define i32 @f30(i32 %foo) {
; ...and again with i64.
define i64 @f31(i64 %foo) {
; CHECK-LABEL: f31:
-; CHECK: risbg %r2, %r2, 0, 140, 50
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 0, 140, 50
+; CHECK-NEXT: br %r14
%and = and i64 %foo, 32766
%shl = shl i64 %and, 50
ret i64 %shl
@@ -360,8 +397,10 @@ define i64 @f31(i64 %foo) {
; We can't use RISBG for the shift in that case.
define i32 @f32(i32 %foo) {
; CHECK-LABEL: f32:
-; CHECK: sll %r2
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: nilf %r2, 4194297
+; CHECK-NEXT: sll %r2, 10
+; CHECK-NEXT: br %r14
%and = and i32 %foo, -7
%shl = shl i32 %and, 10
ret i32 %shl
@@ -370,8 +409,12 @@ define i32 @f32(i32 %foo) {
; ...and again with i64.
define i64 @f33(i64 %foo) {
; CHECK-LABEL: f33:
-; CHECK: sllg %r2
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: llihf %r0, 4194303
+; CHECK-NEXT: oilf %r0, 4294967289
+; CHECK-NEXT: ngr %r0, %r2
+; CHECK-NEXT: sllg %r2, %r0, 10
+; CHECK-NEXT: br %r14
%and = and i64 %foo, -7
%shl = shl i64 %and, 10
ret i64 %shl
@@ -380,8 +423,9 @@ define i64 @f33(i64 %foo) {
; Test a case where the AND comes before a shift right.
define i32 @f34(i32 %foo) {
; CHECK-LABEL: f34:
-; CHECK: risblg %r2, %r2, 25, 159, 55
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risblg %r2, %r2, 25, 159, 55
+; CHECK-NEXT: br %r14
%and = and i32 %foo, 65535
%shl = lshr i32 %and, 9
ret i32 %shl
@@ -390,8 +434,9 @@ define i32 @f34(i32 %foo) {
; ...and again with i64.
define i64 @f35(i64 %foo) {
; CHECK-LABEL: f35:
-; CHECK: risbg %r2, %r2, 57, 191, 55
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r2, %r2, 57, 191, 55
+; CHECK-NEXT: br %r14
%and = and i64 %foo, 65535
%shl = lshr i64 %and, 9
ret i64 %shl
@@ -401,8 +446,10 @@ define i64 @f35(i64 %foo) {
; We can't use RISBG for the shift in that case.
define i32 @f36(i32 %foo) {
; CHECK-LABEL: f36:
-; CHECK: srl %r2
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: nill %r2, 65510
+; CHECK-NEXT: srl %r2, 1
+; CHECK-NEXT: br %r14
%and = and i32 %foo, -25
%shl = lshr i32 %and, 1
ret i32 %shl
@@ -411,8 +458,10 @@ define i32 @f36(i32 %foo) {
; ...and again with i64.
define i64 @f37(i64 %foo) {
; CHECK-LABEL: f37:
-; CHECK: srlg %r2
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: nill %r2, 65510
+; CHECK-NEXT: srlg %r2, %r2, 1
+; CHECK-NEXT: br %r14
%and = and i64 %foo, -25
%shl = lshr i64 %and, 1
ret i64 %shl
@@ -422,9 +471,10 @@ define i64 @f37(i64 %foo) {
; use RISBG there.
define i64 @f38(i64 %foo) {
; CHECK-LABEL: f38:
-; CHECK: srag {{%r[0-5]}}
-; CHECK: sllg {{%r[0-5]}}
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srag %r0, %r2, 32
+; CHECK-NEXT: sllg %r2, %r0, 5
+; CHECK-NEXT: br %r14
%ashr = ashr i64 %foo, 32
%shl = shl i64 %ashr, 5
ret i64 %shl
@@ -433,9 +483,11 @@ define i64 @f38(i64 %foo) {
; Try a similar thing in which no shifted sign bits are kept.
define i64 @f39(i64 %foo, i64 *%dest) {
; CHECK-LABEL: f39:
-; CHECK: srag [[REG:%r[01345]]], %r2, 35
-; CHECK: risbg %r2, %r2, 33, 189, 31
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srag %r0, %r2, 35
+; CHECK-NEXT: risbg %r2, %r2, 33, 189, 31
+; CHECK-NEXT: stg %r0, 0(%r3)
+; CHECK-NEXT: br %r14
%ashr = ashr i64 %foo, 35
store i64 %ashr, i64 *%dest
%shl = shl i64 %ashr, 2
@@ -446,9 +498,11 @@ define i64 @f39(i64 %foo, i64 *%dest) {
; ...and again with the next highest shift value, where one sign bit is kept.
define i64 @f40(i64 %foo, i64 *%dest) {
; CHECK-LABEL: f40:
-; CHECK: srag [[REG:%r[01345]]], %r2, 36
-; CHECK: risbg %r2, [[REG]], 33, 189, 2
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: srag %r0, %r2, 36
+; CHECK-NEXT: risbg %r2, %r0, 33, 189, 2
+; CHECK-NEXT: stg %r0, 0(%r3)
+; CHECK-NEXT: br %r14
%ashr = ashr i64 %foo, 36
store i64 %ashr, i64 *%dest
%shl = shl i64 %ashr, 2
@@ -458,9 +512,11 @@ define i64 @f40(i64 %foo, i64 *%dest) {
; Check a case where the result is zero-extended.
define i64 @f41(i32 %a) {
-; CHECK-LABEL: f41
-; CHECK: risbg %r2, %r2, 36, 191, 62
-; CHECK: br %r14
+; CHECK-LABEL: f41:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT: risbg %r2, %r2, 36, 191, 62
+; CHECK-NEXT: br %r14
%shl = shl i32 %a, 2
%shr = lshr i32 %shl, 4
%ext = zext i32 %shr to i64
@@ -472,10 +528,11 @@ define i64 @f41(i32 %a) {
; when testing whether the shifted-in bits of the shift right were significant.
define i64 @f42(i1 %x) {
; CHECK-LABEL: f42:
-; CHECK: nilf %r2, 1
-; CHECK: lcr %r0, %r2
-; CHECK: llgcr %r2, %r0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: nilf %r2, 1
+; CHECK-NEXT: lcr %r0, %r2
+; CHECK-NEXT: llgcr %r2, %r0
+; CHECK-NEXT: br %r14
%ext = sext i1 %x to i8
%ext2 = zext i8 %ext to i64
ret i64 %ext2
@@ -485,8 +542,10 @@ define i64 @f42(i1 %x) {
; Note that this cannot use RISBLG, but should use RISBG.
define signext i32 @f43(i64 %x) {
; CHECK-LABEL: f43:
-; CHECK: risbg [[REG:%r[0-5]]], %r2, 32, 189, 52
-; CHECK: lgfr %r2, [[REG]]
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r0, %r2, 32, 189, 52
+; CHECK-NEXT: lgfr %r2, %r0
+; CHECK-NEXT: br %r14
%shr3 = lshr i64 %x, 12
%shr3.tr = trunc i64 %shr3 to i32
%conv = and i32 %shr3.tr, -4
@@ -496,7 +555,11 @@ define signext i32 @f43(i64 %x) {
; Check that we don't get the case where the 32-bit and mask is not contiguous
define signext i32 @f44(i64 %x) {
; CHECK-LABEL: f44:
-; CHECK: srlg [[REG:%r[0-5]]], %r2, 12
+; CHECK: # %bb.0:
+; CHECK-NEXT: srlg %r2, %r2, 12
+; CHECK-NEXT: lghi %r0, 10
+; CHECK-NEXT: ngr %r2, %r0
+; CHECK-NEXT: br %r14
%shr4 = lshr i64 %x, 12
%conv = trunc i64 %shr4 to i32
%and = and i32 %conv, 10
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