[llvm] 39cecab - [AArch64][ASMParser] Refuse equal source/destination for LDRAA/LDRAB

[via llvm-commits]

Author: Pierre-vh
Date: 2020-02-19T14:15:17Z
New Revision: 39cecabece8c705187b50612ae5db8748f07b5be

URL: https://github.com/llvm/llvm-project/commit/39cecabece8c705187b50612ae5db8748f07b5be
DIFF: https://github.com/llvm/llvm-project/commit/39cecabece8c705187b50612ae5db8748f07b5be.diff

LOG: [AArch64][ASMParser] Refuse equal source/destination for LDRAA/LDRAB

Differential Revision: https://reviews.llvm.org/D74822

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    llvm/test/MC/AArch64/armv8.3a-diagnostics.s
    llvm/test/MC/AArch64/armv8.3a-signed-pointer.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 29b0d8c6dd3e..578ffb4e42ba 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -4114,6 +4114,16 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
                    "unpredictable STXP instruction, status is also a source");
     break;
   }
+  case AArch64::LDRABwriteback:
+  case AArch64::LDRAAwriteback: {
+    unsigned Xt = Inst.getOperand(0).getReg();
+    unsigned Xn = Inst.getOperand(1).getReg();
+    if (Xt == Xn)
+      return Error(Loc[0],
+          "unpredictable LDRA instruction, writeback base"
+          " is also a destination");
+    break;
+  }
   }
 
 

diff  --git a/llvm/test/MC/AArch64/armv8.3a-diagnostics.s b/llvm/test/MC/AArch64/armv8.3a-diagnostics.s
index fe1ce3068eed..178a64266f26 100644
--- a/llvm/test/MC/AArch64/armv8.3a-diagnostics.s
+++ b/llvm/test/MC/AArch64/armv8.3a-diagnostics.s
@@ -18,3 +18,15 @@
 // CHECK: error: index must be a multiple of 8 in range [-4096, 4088].
   ldrab x0, [x1, 4086]
 // CHECK: error: index must be a multiple of 8 in range [-4096, 4088].
+  ldraa x0, [x0, -4096]!
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable LDRA instruction, writeback base is also a destination
+  ldrab x0, [x0, -4096]!
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable LDRA instruction, writeback base is also a destination
+  ldraa xzr, [xzr, -4096]!
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+  ldraa sp, [sp, -4096]!
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+  ldrab xzr, [xzr, -4096]!
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+  ldrab sp, [sp, -4096]!
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

diff  --git a/llvm/test/MC/AArch64/armv8.3a-signed-pointer.s b/llvm/test/MC/AArch64/armv8.3a-signed-pointer.s
index 07e3783e1dc4..b804889726e7 100644
--- a/llvm/test/MC/AArch64/armv8.3a-signed-pointer.s
+++ b/llvm/test/MC/AArch64/armv8.3a-signed-pointer.s
@@ -327,3 +327,11 @@
 // CHECK-NEXT: ldrab x0, [x1, #0]!  // encoding: [0x20,0x0c,0xa0,0xf8]
 // CHECK-REQ: error: instruction requires: pa
 // CHECK-REQ-NEXT:  ldrab x0, [x1]!
+  ldraa xzr, [sp, -4096]!
+// CHECK-NEXT: ldraa xzr, [sp, #-4096]!  // encoding: [0xff,0x0f,0x60,0xf8]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  ldraa xzr, [sp, -4096]!
+  ldrab xzr, [sp, -4096]!
+// CHECK-NEXT: ldrab xzr, [sp, #-4096]!  // encoding: [0xff,0x0f,0xe0,0xf8]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  ldrab xzr, [sp, -4096]!