[PATCH] D74796: [tablegen] Add !iscomplete(Value)
Nicolai Hähnle via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 19 04:08:01 PST 2020
nhaehnle added a comment.
I like this direction. Please add `!iscomplete` to the documentation, plus some more comments inline.
================
Comment at: llvm/test/TableGen/field-access-initializers.td:11
// CHECK: def B1 {
-// CHECK: string value = A1.value;
+// CHECK: string value = ?;
// CHECK: }
----------------
Thank you, this makes much more sense.
================
Comment at: llvm/test/TableGen/isa-consistency.td:33
+
+// So far so good, but it doesn't work without the field assignment.
+// CHECK: def Z4 {
----------------
That comment is out of place now, isn't it?
================
Comment at: llvm/test/TableGen/isa-consistency.td:50
+
+// Yet it does work on bits<>, even though it didn't work on bit.
+// CHECK: def Z6 {
----------------
Same.
================
Comment at: llvm/test/TableGen/isa-consistency.td:59-60
+
+// Stranger still, if you extract an unset bit from a bits<> it still works even
+// though bit didn't.
+// CHECK: def Z7 {
----------------
Same.
================
Comment at: llvm/test/TableGen/iscomplete.td:159-161
+ // This one however, caused an assertion because BitC's value an UnsetInit
+ // and !eq() can only accept TypedInit's.
+ // bit D = !if(!eq(Inputs.BitC, 0), 1, 0);
----------------
It doesn't assert, does it? Rather it produces an error message.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D74796/new/
https://reviews.llvm.org/D74796
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