[PATCH] D67694: [Power9] Fix the missing pseudo instruction scheduling information for power9
qshanz via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 18 21:38:20 PST 2020
steven.zhang added a comment.
If we didn't clear the hasNoSchedulingInfo for instructions, it didn't need to provide the scheduling information even we mark the model as complete. And that will result in some instructions scheduling info missing. I.e. for the pseudo load(LDtocL), it will use the default latency specified in the SchedModel, that is 5 cycles. And now, it is correct to 4 cycles.
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Comment at: llvm/lib/Target/PowerPC/PPCInstrFormats.td:2168
class PPCPostRAExpPseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
- : PPCEmitTimePseudo<OOL, IOL, asmstr, pattern> {
+ : PPCEmitTimePseudoWithSchedInfo<OOL, IOL, asmstr, pattern> {
let isPseudo = 1;
----------------
jsji wrote:
> We did have SchedInfo in `P9InstrResources.td` before, so are they ignored? and always using the default latency?
>
No, it will still use the latency that we specify in the resources.td. The bit here affect the checker.
Repository:
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https://reviews.llvm.org/D67694/new/
https://reviews.llvm.org/D67694
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