[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

[Evandro Menezes via Phabricator via llvm-commits]

evandro added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCV.td:54
+    : SubtargetFeature<"v", "HasStdExtV", "true",
+                       "'V' (Vector Instructions)">;
+def HasStdExtV : Predicate<"Subtarget->hasStdExtV()">,
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rogfer01 wrote:
> evandro wrote:
> > HsiangKai wrote:
> > > evandro wrote:
> > > > Should it also imply `FeatureStdExtD`?
> > > I didn't find that V will imply D extension. Could you indicate the description in spec about this?
> > Indeed it doesn't:
> > 
> > > If the base scalar ISA does not include floating-point, then a `fcsr` register is also added to hold mirrors of the `vxsat` and `vxrm` CSRs as explained below.
> > 
> > Which means that the instructions that take FP scalars should also depend on `hasStdExt{F|D}`.  Likewise when the scalar is a 64 bit integer, `hasRV64`.
> I don't think we have to do anything special with 64 bit: section 11.1 states what is the behaviour when `XLEN` is different than `SEW`.
Good point. 👍🏻


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https://reviews.llvm.org/D69987