[PATCH] D74471: [AArch64][SVE] Add predicate reinterpret intrinsics

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added a comment.

In D74471#1872978 <https://reviews.llvm.org/D74471#1872978>, @efriedma wrote:

> When you convert from `<vscale x 2 x i1>` to `<vscale x 16 x i1>` using sve.convert.to.svbool, what values do the other bits contain?  Zero?  Poison?  Something else?


When converting from `<vscale x 2 x i1>` to `svbool_t`, the other lanes are defined as zero.

As you probably spotted, this implementation does not actually guarantee that those lanes are zeroed. At the moment though, this is not really a problem because there are no optimizations on these intrinsics that rely on this definition and the instructions themselves produce predicates where the lanes are zeroed implicitly. If we don't fold the zeroing operation into the instruction that implicitly zeroes the lanes, there is a performance penalty, so we should write some peephole pass to remove the unnecessary instructions.

We can either choose to:

- Add the explicit zeroing in this patch and optimise these away later.
- Leave the patch as-is for now - given that it doesn't break anything - and do this in a follow-up patch (adding a TODO to the list: https://docs.google.com/document/d/1Psr3s3eh9PUlrpkuU7OKOi8my7xSt_v1BvjoQpbAGXc)

Without having properly discussed this and deciding on which way to go, my LGTM was probably a bit premature. Sorry for that!


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