[llvm] d6eef06 - [TargetLowering] Add SimplifyMultipleUseDemandedBits 'all elements' helper wrapper. NFC.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 18 11:54:15 PST 2020
Author: Simon Pilgrim
Date: 2020-02-18T19:53:50Z
New Revision: d6eef0614fe7e724b3eeb5598619dd6a657905a4
URL: https://github.com/llvm/llvm-project/commit/d6eef0614fe7e724b3eeb5598619dd6a657905a4
DIFF: https://github.com/llvm/llvm-project/commit/d6eef0614fe7e724b3eeb5598619dd6a657905a4.diff
LOG: [TargetLowering] Add SimplifyMultipleUseDemandedBits 'all elements' helper wrapper. NFC.
Added:
Modified:
llvm/include/llvm/CodeGen/TargetLowering.h
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 4a28f1966b7b..abc4473fcac8 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -3239,7 +3239,7 @@ class TargetLowering : public TargetLoweringBase {
/// Helper wrapper around SimplifyDemandedBits.
/// Adds Op back to the worklist upon success.
- bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
+ bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
DAGCombinerInfo &DCI) const;
/// More limited version of SimplifyDemandedBits that can be used to "look
@@ -3250,6 +3250,12 @@ class TargetLowering : public TargetLoweringBase {
SelectionDAG &DAG,
unsigned Depth) const;
+ /// Helper wrapper around SimplifyMultipleUseDemandedBits, demanding all
+ /// elements.
+ SDValue SimplifyMultipleUseDemandedBits(SDValue Op, const APInt &DemandedBits,
+ SelectionDAG &DAG,
+ unsigned Depth = 0) const;
+
/// Look at Vector Op. At this point, we know that only the DemandedElts
/// elements of the result of Op are ever used downstream. If we can use
/// this information to simplify Op, create a new simplified DAG node and
@@ -3284,6 +3290,7 @@ class TargetLowering : public TargetLoweringBase {
const APInt &DemandedElts,
const SelectionDAG &DAG,
unsigned Depth = 0) const;
+
/// Determine which of the bits specified in Mask are known to be either zero
/// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
/// argument allows us to only collect the known bits that are shared by the
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 9455797310fb..5a38207e41cf 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -790,6 +790,17 @@ SDValue TargetLowering::SimplifyMultipleUseDemandedBits(
return SDValue();
}
+SDValue TargetLowering::SimplifyMultipleUseDemandedBits(
+ SDValue Op, const APInt &DemandedBits, SelectionDAG &DAG,
+ unsigned Depth) const {
+ EVT VT = Op.getValueType();
+ APInt DemandedElts = VT.isVector()
+ ? APInt::getAllOnesValue(VT.getVectorNumElements())
+ : APInt(1, 1);
+ return SimplifyMultipleUseDemandedBits(Op, DemandedBits, DemandedElts, DAG,
+ Depth);
+}
+
/// Look at Op. At this point, we know that only the OriginalDemandedBits of the
/// result of Op are ever used downstream. If we can use this information to
/// simplify Op, create a new simplified DAG node and return true, returning the
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 385cb754731b..9cb3fe58730b 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -38426,15 +38426,10 @@ static SDValue combineVSelectToBLENDV(SDNode *N, SelectionDAG &DAG,
}
// Otherwise we can still at least try to simplify multiple use bits.
- APInt DemandedMask(APInt::getSignMask(BitWidth));
- APInt DemandedElts(APInt::getAllOnesValue(VT.getVectorNumElements()));
- KnownBits Known;
- TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
- !DCI.isBeforeLegalizeOps());
- if (SDValue V = TLI.SimplifyMultipleUseDemandedBits(Cond, DemandedMask,
- DemandedElts, DAG, 0))
- return DAG.getNode(X86ISD::BLENDV, SDLoc(N), N->getValueType(0),
- V, N->getOperand(1), N->getOperand(2));
+ APInt DemandedBits(APInt::getSignMask(BitWidth));
+ if (SDValue V = TLI.SimplifyMultipleUseDemandedBits(Cond, DemandedBits, DAG))
+ return DAG.getNode(X86ISD::BLENDV, SDLoc(N), N->getValueType(0), V,
+ N->getOperand(1), N->getOperand(2));
return SDValue();
}
@@ -42184,9 +42179,8 @@ static SDValue combineMaskedStore(SDNode *N, SelectionDAG &DAG,
APInt DemandedBits(APInt::getSignMask(VT.getScalarSizeInBits()));
if (TLI.SimplifyDemandedBits(Mask, DemandedBits, DCI))
return SDValue(N, 0);
- APInt DemandedElts = APInt::getAllOnesValue(VT.getVectorNumElements());
- if (SDValue NewMask = TLI.SimplifyMultipleUseDemandedBits(
- Mask, DemandedBits, DemandedElts, DAG, 0))
+ if (SDValue NewMask =
+ TLI.SimplifyMultipleUseDemandedBits(Mask, DemandedBits, DAG))
return DAG.getMaskedStore(Mst->getChain(), SDLoc(N), Mst->getValue(),
Mst->getBasePtr(), Mst->getOffset(), NewMask,
Mst->getMemoryVT(), Mst->getMemOperand(),
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