[PATCH] D74649: [TBLGEN] Emit register pressure set enum

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGb2a958a01385: [TBLGEN] Emit register pressure set enum (authored by rampitec).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74649/new/

https://reviews.llvm.org/D74649

Files:
  llvm/test/TableGen/Common/reg-with-subregs-common.td
  llvm/test/TableGen/pset-enum.td
  llvm/utils/TableGen/CodeGenRegisters.cpp
  llvm/utils/TableGen/RegisterInfoEmitter.cpp


Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp
===================================================================
--- llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -182,6 +182,20 @@
       OS << "} // end namespace " << Namespace << "\n\n";
   }
 
+  OS << "// Register pressure sets enum.\n";
+  if (!Namespace.empty())
+    OS << "namespace " << Namespace << " {\n";
+  OS << "enum RegisterPressureSets {\n";
+  unsigned NumSets = Bank.getNumRegPressureSets();
+  for (unsigned i = 0; i < NumSets; ++i ) {
+    const RegUnitSet &RegUnits = Bank.getRegSetAt(i);
+    OS << "  " << RegUnits.Name << " = " << i << ",\n";
+  }
+  OS << "};\n";
+  if (!Namespace.empty())
+    OS << "} // end namespace " << Namespace << '\n';
+  OS << '\n';
+
   OS << "} // end namespace llvm\n\n";
   OS << "#endif // GET_REGINFO_ENUM\n\n";
 }
Index: llvm/utils/TableGen/CodeGenRegisters.cpp
===================================================================
--- llvm/utils/TableGen/CodeGenRegisters.cpp
+++ llvm/utils/TableGen/CodeGenRegisters.cpp
@@ -1956,7 +1956,7 @@
       // Speculatively grow the RegUnitSets to hold the new set.
       RegUnitSets.resize(RegUnitSets.size() + 1);
       RegUnitSets.back().Name =
-        RegUnitSets[Idx].Name + "+" + RegUnitSets[SearchIdx].Name;
+        RegUnitSets[Idx].Name + "_with_" + RegUnitSets[SearchIdx].Name;
 
       std::set_union(RegUnitSets[Idx].Units.begin(),
                      RegUnitSets[Idx].Units.end(),
Index: llvm/test/TableGen/pset-enum.td
===================================================================
--- /dev/null
+++ llvm/test/TableGen/pset-enum.td
@@ -0,0 +1,11 @@
+// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
+// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common -DUSE_NAMESPACE %s | FileCheck --check-prefixes=CHECK,NAMESPACE %s
+
+include "reg-with-subregs-common.td"
+
+// CHECK-LABEL:    // Register pressure sets enum.
+// NAMESPACE-NEXT: namespace TestNamespace {
+// CHECK-NEXT:     enum RegisterPressureSets {
+// CHECK-NEXT:       GPR32 = 0,
+// CHECK-NEXT:     };
+// NAMESPACE-NEXT: } // end namespace TestNamespace
Index: llvm/test/TableGen/Common/reg-with-subregs-common.td
===================================================================
--- llvm/test/TableGen/Common/reg-with-subregs-common.td
+++ llvm/test/TableGen/Common/reg-with-subregs-common.td
@@ -16,6 +16,9 @@
            !listconcat(acc, !if(!lt(cur, N), [cur], [])));
 }
 
+#ifdef USE_NAMESPACE
+  let Namespace = "TestNamespace" in {
+#endif
 foreach Index = 0-31 in {
   def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
 }
@@ -35,6 +38,9 @@
 foreach Index = 0-255 in {
   def R#Index : Register <"r"#Index>;
 }
+#ifdef USE_NAMESPACE
+}
+#endif
 
 def GPR32 : RegisterClass<"TestTarget", [i32], 32,
                           (add (sequence "R%u", 0, 255))>;
@@ -124,5 +130,11 @@
                               (decimate (shl GPR32, 31), 1)
                              ]>;
 
+#ifdef USE_NAMESPACE
+  let Namespace = "TestNamespace" in {
+#endif
 def GPR_64 : RegisterClass<"", [v2i32], 64, (add GPR64)>;
 def GPR_1024 : RegisterClass<"", [v32i32], 1024, (add GPR1024)>;
+#ifdef USE_NAMESPACE
+}
+#endif


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