[llvm] 68b49f7 - [ARM,MVE] Add intrinsics vclzq and vclsq.
Simon Tatham via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 18 01:36:42 PST 2020
Author: Simon Tatham
Date: 2020-02-18T09:34:50Z
New Revision: 68b49f7ef49eec068b7ddcf86c868e2a193e64e1
URL: https://github.com/llvm/llvm-project/commit/68b49f7ef49eec068b7ddcf86c868e2a193e64e1
DIFF: https://github.com/llvm/llvm-project/commit/68b49f7ef49eec068b7ddcf86c868e2a193e64e1.diff
LOG: [ARM,MVE] Add intrinsics vclzq and vclsq.
Summary:
vclzq maps nicely to the existing target-independent @llvm.ctlz IR
intrinsic. But vclsq ('count leading sign bits') has no corresponding
target-independent intrinsic, so I've made up @llvm.arm.mve.vcls.
This commit adds the unpredicated forms only.
Reviewers: dmgreen, miyuki, MarkMurrayARM, ostannard
Reviewed By: miyuki
Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D74335
Added:
clang/test/CodeGen/arm-mve-intrinsics/vclz.c
llvm/test/CodeGen/Thumb2/mve-intrinsics/vcls.ll
Modified:
clang/include/clang/Basic/arm_mve.td
clang/include/clang/Basic/arm_mve_defs.td
llvm/include/llvm/IR/IntrinsicsARM.td
llvm/lib/Target/ARM/ARMInstrMVE.td
Removed:
################################################################################
diff --git a/clang/include/clang/Basic/arm_mve.td b/clang/include/clang/Basic/arm_mve.td
index 126c2e2214ae..21801b4d448e 100644
--- a/clang/include/clang/Basic/arm_mve.td
+++ b/clang/include/clang/Basic/arm_mve.td
@@ -237,8 +237,11 @@ let params = T.Unsigned in {
let params = T.Int in {
def vmvnq: Intrinsic<Vector, (args Vector:$a),
(xor $a, (uint_max Vector))>;
+ def vclzq: Intrinsic<Vector, (args Vector:$a),
+ (IRIntBase<"ctlz", [Vector]> $a, (i1 0))>;
}
let params = T.Signed in {
+ def vclsq: Intrinsic<Vector, (args Vector:$a), (IRInt<"vcls", [Vector]> $a)>;
def vnegq: Intrinsic<Vector, (args Vector:$a),
(sub (zeroinit Vector), $a)>;
def vabsq: Intrinsic<Vector, (args Vector:$a),
diff --git a/clang/include/clang/Basic/arm_mve_defs.td b/clang/include/clang/Basic/arm_mve_defs.td
index 9f245d0436c4..9e5b7b32c511 100644
--- a/clang/include/clang/Basic/arm_mve_defs.td
+++ b/clang/include/clang/Basic/arm_mve_defs.td
@@ -129,6 +129,12 @@ def vrev: CGHelperFn<"ARMMVEVectorElementReverse"> {
let special_params = [IRBuilderIntParam<1, "unsigned">];
}
+// Helper for making boolean flags in IR
+def i1: IRBuilderBase {
+ let prefix = "llvm::ConstantInt::get(Builder.getInt1Ty(), ";
+ let special_params = [IRBuilderIntParam<0, "bool">];
+}
+
// A node that makes an Address out of a pointer-typed Value, by
// providing an alignment as the second argument.
def address;
diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vclz.c b/clang/test/CodeGen/arm-mve-intrinsics/vclz.c
new file mode 100644
index 000000000000..7a2ebe0a627a
--- /dev/null
+++ b/clang/test/CodeGen/arm-mve-intrinsics/vclz.c
@@ -0,0 +1,132 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+
+#include <arm_mve.h>
+
+// CHECK-LABEL: @test_vclzq_s8(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> [[A:%.*]], i1 false)
+// CHECK-NEXT: ret <16 x i8> [[TMP0]]
+//
+int8x16_t test_vclzq_s8(int8x16_t a)
+{
+#ifdef POLYMORPHIC
+ return vclzq(a);
+#else /* POLYMORPHIC */
+ return vclzq_s8(a);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vclzq_s16(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> [[A:%.*]], i1 false)
+// CHECK-NEXT: ret <8 x i16> [[TMP0]]
+//
+int16x8_t test_vclzq_s16(int16x8_t a)
+{
+#ifdef POLYMORPHIC
+ return vclzq(a);
+#else /* POLYMORPHIC */
+ return vclzq_s16(a);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vclzq_s32(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> [[A:%.*]], i1 false)
+// CHECK-NEXT: ret <4 x i32> [[TMP0]]
+//
+int32x4_t test_vclzq_s32(int32x4_t a)
+{
+#ifdef POLYMORPHIC
+ return vclzq(a);
+#else /* POLYMORPHIC */
+ return vclzq_s32(a);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vclzq_u8(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> [[A:%.*]], i1 false)
+// CHECK-NEXT: ret <16 x i8> [[TMP0]]
+//
+uint8x16_t test_vclzq_u8(uint8x16_t a)
+{
+#ifdef POLYMORPHIC
+ return vclzq(a);
+#else /* POLYMORPHIC */
+ return vclzq_u8(a);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vclzq_u16(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> [[A:%.*]], i1 false)
+// CHECK-NEXT: ret <8 x i16> [[TMP0]]
+//
+uint16x8_t test_vclzq_u16(uint16x8_t a)
+{
+#ifdef POLYMORPHIC
+ return vclzq(a);
+#else /* POLYMORPHIC */
+ return vclzq_u16(a);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vclzq_u32(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> [[A:%.*]], i1 false)
+// CHECK-NEXT: ret <4 x i32> [[TMP0]]
+//
+uint32x4_t test_vclzq_u32(uint32x4_t a)
+{
+#ifdef POLYMORPHIC
+ return vclzq(a);
+#else /* POLYMORPHIC */
+ return vclzq_u32(a);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vclsq_s8(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8> [[A:%.*]])
+// CHECK-NEXT: ret <16 x i8> [[TMP0]]
+//
+int8x16_t test_vclsq_s8(int8x16_t a)
+{
+#ifdef POLYMORPHIC
+ return vclsq(a);
+#else /* POLYMORPHIC */
+ return vclsq_s8(a);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vclsq_s16(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16> [[A:%.*]])
+// CHECK-NEXT: ret <8 x i16> [[TMP0]]
+//
+int16x8_t test_vclsq_s16(int16x8_t a)
+{
+#ifdef POLYMORPHIC
+ return vclsq(a);
+#else /* POLYMORPHIC */
+ return vclsq_s16(a);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vclsq_s32(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32> [[A:%.*]])
+// CHECK-NEXT: ret <4 x i32> [[TMP0]]
+//
+int32x4_t test_vclsq_s32(int32x4_t a)
+{
+#ifdef POLYMORPHIC
+ return vclsq(a);
+#else /* POLYMORPHIC */
+ return vclsq_s32(a);
+#endif /* POLYMORPHIC */
+}
+
diff --git a/llvm/include/llvm/IR/IntrinsicsARM.td b/llvm/include/llvm/IR/IntrinsicsARM.td
index 80ab3a73d391..0e8a5239119d 100644
--- a/llvm/include/llvm/IR/IntrinsicsARM.td
+++ b/llvm/include/llvm/IR/IntrinsicsARM.td
@@ -1161,5 +1161,7 @@ defm int_arm_mve_vcvt_fix: MVEMXPredicated<
def int_arm_mve_vrintn: Intrinsic<
[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
+def int_arm_mve_vcls: Intrinsic<
+ [llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
} // end TargetPrefix
diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td
index b0ec20494b8a..0583a26dffea 100644
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -2076,6 +2076,13 @@ let Predicates = [HasMVEInt] in {
(v4i32 ( MVE_VCLZs32 (v4i32 MQPR:$val1)))>;
def : Pat<(v8i16 ( ctlz (v8i16 MQPR:$val1))),
(v8i16 ( MVE_VCLZs16 (v8i16 MQPR:$val1)))>;
+
+ def : Pat<(v16i8 ( int_arm_mve_vcls (v16i8 MQPR:$val1))),
+ (v16i8 ( MVE_VCLSs8 (v16i8 MQPR:$val1)))>;
+ def : Pat<(v4i32 ( int_arm_mve_vcls (v4i32 MQPR:$val1))),
+ (v4i32 ( MVE_VCLSs32 (v4i32 MQPR:$val1)))>;
+ def : Pat<(v8i16 ( int_arm_mve_vcls (v8i16 MQPR:$val1))),
+ (v8i16 ( MVE_VCLSs16 (v8i16 MQPR:$val1)))>;
}
class MVE_VABSNEG_int<string iname, string suffix, bits<2> size, bit negate,
diff --git a/llvm/test/CodeGen/Thumb2/mve-intrinsics/vcls.ll b/llvm/test/CodeGen/Thumb2/mve-intrinsics/vcls.ll
new file mode 100644
index 000000000000..788bf32a2fb7
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/mve-intrinsics/vcls.ll
@@ -0,0 +1,36 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
+
+define arm_aapcs_vfpcc <16 x i8> @test_vclsq_s8(<16 x i8> %a) {
+; CHECK-LABEL: test_vclsq_s8:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vcls.s8 q0, q0
+; CHECK-NEXT: bx lr
+entry:
+ %0 = tail call <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8> %a)
+ ret <16 x i8> %0
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vclsq_s16(<8 x i16> %a) {
+; CHECK-LABEL: test_vclsq_s16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vcls.s16 q0, q0
+; CHECK-NEXT: bx lr
+entry:
+ %0 = tail call <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16> %a)
+ ret <8 x i16> %0
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vclsq_s32(<4 x i32> %a) {
+; CHECK-LABEL: test_vclsq_s32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vcls.s32 q0, q0
+; CHECK-NEXT: bx lr
+entry:
+ %0 = tail call <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32> %a)
+ ret <4 x i32> %0
+}
+
+declare <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8>)
+declare <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16>)
+declare <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32>)
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