[PATCH] D70771: [PowerPC] Replace the PPCISD:: SExtVElems with ISD::SIGN_EXTEND_INREG to leverage the combine rules

[qshanz via Phabricator via llvm-commits]

steven.zhang added a comment.

In D70771#1880012 <https://reviews.llvm.org/D70771#1880012>, @lkail wrote:

> > We are combing the instructions into sext_inreg instead of Power specific node SExtVElems, and then, it is selected as hw instruction which is defined in the pattern td.
>
> CMIIW, `SExtVElems` works on types that fit in a vector register, like `v16i8`. And according to codes `SExtVElems` generates, it intends to sext lower bits of target element type in-place, which suggests `SIGN_EXTEND_INREG`.


Yes, it is doing something like: a << N >> N; The SExtVElems has the same semantics with SIGN_EXTEND_INREG if its type is vector.


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  https://reviews.llvm.org/D70771/new/

https://reviews.llvm.org/D70771