[PATCH] D72758: Add OffsetIsScalable to getMemOperandWithOffset

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen marked 2 inline comments as done.
sdesmalen added inline comments.


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Comment at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1245
                                        int64_t &Offset,
+                                       bool &OffsetIsScalable,
                                        const TargetRegisterInfo *TRI) const {
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efriedma wrote:
> sdesmalen wrote:
> > efriedma wrote:
> > > I'm not sure why this modification is necessary.  The offset doesn't actually scale, does it?  The width of memory operation does, but getMemOperandWithOffset doesn't return that anyway.
> > For e.g. `AArch64::LDR_ZXI` and `AArch64::STR_ZXI`, it is actually the offset that is scaled by VL elements (i.e. load/store at `ptr + (N * sizeof(vector)`).
> Oh, that makes sense.
> 
> I guess there are theoretically two separate dimensions: whether the width is scalable, and whether the offset is scalable.  For SVE, I guess those happen to be the same for all the defined instructions?
Yes, that's correct.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72758/new/

https://reviews.llvm.org/D72758