[PATCH] D72676: [PowerPC] Add the missing InstrAliasing for 64-bit rotate instructions

[qshanz via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG113df90388d8: [PowerPC] Add the missing InstrAliasing for 64-bit rotate instructions (authored by steven.zhang).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72676/new/

https://reviews.llvm.org/D72676

Files:
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/test/CodeGen/PowerPC/bperm.ll


Index: llvm/test/CodeGen/PowerPC/bperm.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/bperm.ll
+++ llvm/test/CodeGen/PowerPC/bperm.ll
@@ -9,7 +9,7 @@
   ret i32 %0
 
 ; CHECK-LABEL: @bs4
-; CHECK: rlwinm [[REG1:[0-9]+]], 3, 8, 0, 31
+; CHECK: rotlwi [[REG1:[0-9]+]], 3, 8
 ; CHECK: rlwimi [[REG1]], 3, 24, 16, 23
 ; CHECK: rlwimi [[REG1]], 3, 24, 0, 7
 ; CHECK: mr 3, [[REG1]]
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -909,6 +909,10 @@
 }  // hasSideEffects = 0
 }  // End FXU Operations.
 
+def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>;
+def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>;
+def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>;
+def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>;
 
 //===----------------------------------------------------------------------===//
 // Load/Store instructions.


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D72676.244918.patch
Type: text/x-patch
Size: 1186 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200217/07b33419/attachment.bin>